A simple (audio) synthesizer on the iCEBreaker FPGA.

A collection of modern/faster/saner alternatives to common unix commands.

Windows inside a Docker container.

Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.

Checks the PDFs submitted to a conference, e.g., for formatting violations and double anonymous violations

Convert TensorFlow Lite models (*.tflite) to ONNX.

Exploration of the microarchitecture on the banana-pi3 (RISCV)

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

OpenVADL extension for Visual Studio Code

An open-source implementation of the VADL processor description language.

Tool to autogen LLVM X86 scheduling model.

Extendable Translating Instruction Set Simulator

A GitHub action to create a repository dispatch event

Chisel RISC-V Vector 1.0 Implementation

Open-source high-performance RISC-V processor

Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study

Implementation of RISC-V P/ZCE extension for GCC backend

Test cases for RISC-V P extension. Modified from the repo of Andestech.

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

Buildah assets for making the riscv_dev container

CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices

RISC-V Zve32x Vector Coprocessor

RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor

Benchmarking of Vicuna 2.0 using MLPerfTiny Benchmarks