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1. cellrv32 cellrv32 Public

   A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor …

   SystemVerilog 3 1

2. github-beginer github-beginer Public

   SystemVerilog

3. apb_timer apb_timer Public

   Verilog

4. cellrv32-riscof cellrv32-riscof Public

   RISCOF platform to check the CELLRV32 for RISC-V ISA compatibility.

   VHDL

5. NN_RGB_FLAPPY_BIRD NN_RGB_FLAPPY_BIRD Public

   🐦 A game of flappy bird for one player, plays by controlling the bird using a hand tracking mechanism

   SystemVerilog

6. SNC_core SNC_core Public

   SystemVerilog