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1. FPGA-Based-TPU FPGA-Based-TPU Public

   TPU designed on DE1-SoC FPGA for 4096x4096 sparse MM and convolution for UC Davis Senior Design 2023 with Austin York, Gurkirat Dhillon, and Kent Cassidy.

   SystemVerilog 1

2. Chisel-TPU-Parameterized Chisel-TPU-Parameterized Public

   TPU designed using Chisel to support a parameterizable systolic array and input bitwidths, as well as natively supporting convolution. Designed for CSE 228 Agile Hardware Design SQ25 with Ella Lehavi.

   Scala

3. clash_star_tracker clash_star_tracker Public

   Python Program to process Clash of Clans screenshots to track team performance over time leveraging machine learning, adaptive thresholding, and well-designed data structures.

   Python

4. esp-computer-vision esp-computer-vision Public

   Interfacing the ESP32c3 microcontroller with an ArduCAM-M-2MP Camera Shield 2MP SPI Camera to perform image processing and computer vision

   C

5. MIS-Timer MIS-Timer Public

   Given an OPENRoad subcircuit file, this program will use SPICE to simulate worst-case speed-up and slow-down due to the Multiple-Input-Switching effect. Designed for CSE 222B Advanced VLSI SQ25 wit…

   Python

6. dsp-tools dsp-tools Public

   Developing image processing tools for practice and fun.

   Python