Veryl: A Modern Hardware Description Language

A project of short tutorials and how-to guides for Coq features and Coq Platform packages.

Arthur's Formal Metatheory in Coq

Learning FPGA, yosys, nextpnr, and RISC-V

SystemVerilog linter

⏰ PL conference deadline countdowns

Test suite designed to check compliance with the SystemVerilog standard.

Installs Vivado on M1/M2/M3 macs

Catalog of visual lambda calculi

Lecture notes and exercises for the introductory course on domain theory and denotational semantics at the Midlands Graduate School (MGS) 2023

A monadic library for symbolic evaluation

Selected Papers of Dana S. Scott

Tools for FPGA development.

Integrating ReScript and rescript-react into the official Vite React template

The library for web and native user interfaces.

A List of Free and Open Source Hardware Verification Tools and Frameworks

We define a simple programming language, simp_lang, then instantiate Iris to verify simple simp_lang programs with concurrent separation logic.

Concurrent Programming with Effect Handlers

Library to create Coq record update functions

Coq development for the course "Mechanized semantics", Collège de France, 2019-2020

Small command-line program to download videos from some streaming sites.

Icarus Verilog

Verilator open-source SystemVerilog simulator and lint system

Hardware Description Languages

Must-have verilog systemverilog modules

Counterexamples in Type Systems

Phd Thesis of Théo Winterhalter. Look at releases to get the latest PDF.

Workshop on Open-Source EDA Technology (WOSET)