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Pull requests: OpenXiangShan/XiangShan
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submodule(yunsuan): bump yunsuan to fix vfcvt timing
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: timing
To fix bad timing
feat(backend): enhance bju iq with two deq ports, split uop for auipc and jalr, increase fpPreg to 256, robSize and rabSize to 352
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
feat(vmove): add vmove unit
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
feat(pf): add csr control of delay latency for l2 prefetch train
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
feat(prefetch): add load addr statistic in ROB but tlb latency still …
#5121
opened Oct 15, 2025 by
Maxpicca-Li
•
Draft
feat(XSCore): XSCore should not have combinational logics
#5120
opened Oct 15, 2025 by
linjuanZ
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Bump chisel 7.2.0 (should be rebased and merged)
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
module: top
XSTop, XSTile, XSParameters, configs
note: do not squash
(PR) For maintainer: please use rebase-and-merge instead of squash-and-merge
fix(L1TLB): ignore addr when hfence.vvma or sfence.vma when v=1
#5114
opened Oct 14, 2025 by
cebarobot
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feat(L2Top, XSTile): move IntBuffer for beu into L2Top for partition
#5110
opened Oct 14, 2025 by
linjuanZ
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feat(icache,ifu): generate maybeRvc on cache refill & revert temporary 4-stage IFU
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
note: do not squash
(PR) For maintainer: please use rebase-and-merge instead of squash-and-merge
topic: timing
To fix bad timing
feat(ibuffer): only store first met exception
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: area
To reduce area comsuption
feat(bpu): Tage BaseTable and SCTable dual-port SRAM changed to single port with 2bank
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: timing
To fix bad timing
fix(Bpu): remove abtbMeta from BpuMeta and add FastTrain IO
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: code quality
To make code more readable & maintainable
fix(CSR, NMI): fix the logic for gating Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
nmi
module: backend
feat(abtb): support fast predict when s3 override
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: performance
To improve performance
perf(pf): add berti prefetch
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: performance
To improve performance
fix(LoadUnit): Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
tlb.req.kill is only valid when s1_valid
module: memory
timing(LoadQueueReplay): move needReplay generation to LDU
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: timing
To fix bad timing
feat(pdb): add asm and dasm commands for XSPdb
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
#5011
opened Sep 8, 2025 by
SFangYy
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fix(prefetch): the statistic of prefetch hit in v3
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
fix(MMU): PMM is disabled if MXR is effective
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
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