A one transistor (1T-RAM)
bit cell and method for manufacture are provided. A
metal-insulator-
metal (MIM)
capacitor structure and method of manufacturing it in an integrated process that includes a finFET
transistor for the 1T-RAM
bit cell is provided. In some embodiments, the finFET
transistor and MIM
capacitor are formed in a memory region and an asymmetric
processing method is disclosed, which allows planar
MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM
cell and additional transistors may be combined to form a
macro cell, multiple
macro cells may form an
integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the
effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator
layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.