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- ArticleAugust 2004
Low-power carry-select adder using adaptive supply voltage based on input vector patterns
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 313–318https://doi.org/10.1145/1013235.1013312Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. ...
- ArticleAugust 2004
Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 257–262https://doi.org/10.1145/1013235.1013301Dynamic voltage scaling (DVS) is a very effective low-power design technique in modern digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system. This paper ...
- ArticleAugust 2004
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 248–251https://doi.org/10.1145/1013235.1013298In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to ...
- ArticleAugust 2004
Power-optimal pipelining in deep submicron technology
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 218–223https://doi.org/10.1145/1013235.1013291This paper explores the effectiveness of pipelining as a power saving tool, where the reduction in logic depth per stage is used to reduce supply voltage at a fixed clock frequency. We examine power-optimal pipelining in deep submicron technology, both ...
- ArticleAugust 2004
Approaches to run-time and standby mode leakage reduction in global buses
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 188–193https://doi.org/10.1145/1013235.1013285In this paper, we present various design approaches to leakage minimization in global repeaters. We demonstrate the applicability of the MTCMOS scheme to global repeaters for leakage reduction. We then analyze two design approaches called Duplicated ...
- ArticleAugust 2004
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 108–113https://doi.org/10.1145/1013235.1013268We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage.Using the dependence of ...
- ArticleAugust 2004
Nanoscale CMOS circuit leakage power reduction by double-gate device
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 102–107https://doi.org/10.1145/1013235.1013267Leakage power for extremely scaled (Leff = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ...
- ArticleAugust 2004
Device optimization for ultra-low power digital sub-threshold operation
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 96–101https://doi.org/10.1145/1013235.1013266Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of ...
- ArticleAugust 2004
Experimental measurement of a novel power gating structure with intermediate power saving mode
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 20–25https://doi.org/10.1145/1013235.1013246A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and ...
- ArticleAugust 2004
Technology exploration for adaptive power and frequency scaling in 90nm CMOS
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 14–19https://doi.org/10.1145/1013235.1013245In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated ...
- ArticleAugust 2004
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 8–13https://doi.org/10.1145/1013235.1013244This paper examines the effectiveness of larger-than-Vdd forward body bias (FBB) in nanoscale bulk CMOS circuits where Vdd is expected to scale below 0.5V. Equal-to and larger-than Vdd FBB schemes offer unique advantages over conventional FBB such as ...
- ArticleAugust 2004
Managing standby and active mode leakage power in deep sub-micron design
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designPages 274–279https://doi.org/10.1145/1013235.1013239Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band ...