SIGARCH

The papers that follow comprise the proceedings of the first Reconfigurable and Adaptive Architecture Workshop (RAAW 2006) that was held in conjunction with the 39^th International Conference on Microarchitecture in Orlando, Florida.

Hardware accelerators, used as application-specific extensions to the computational capabilities of a system, are efficient mechanisms to enhance the performance and reduce the power dissipation in a System On Chip (SoC). These accelerators execute on ...

Embedded systems designers that use FPGAs are increasingly including soft processors in their designs (configurable processors built in the programmable logic of the FPGA). While there has been a significant amount of research on adding custom ...

With reducing feature sizes, more transistors can be integrated on the chip. The increased transistor budget can be utilized to improve the instruction level parallelism (ILP) exploited from the processor. However, the transistors cannot be used to ...

Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such approaches are prone to a fundamental trade-off between the architectural ...

This column consists of selected traffic from the comp.arch newsgroup, a forum for discussion of computer architecture on the Internet---an international computer network.

As always, the opinions expressed in this column are the personal views of the ...