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Volume 13, Issue 12December 2005
Publisher:
  • IEEE Educational Activities Department
  • 445 Hoes Lane P.O. Box 1331 Piscataway, NJ
  • United States
ISSN:1063-8210
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research-article
Fast comparisons of circuit implementations

Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet ...

research-article
Wire retiming as fixpoint computation

In system-on-chips (SOCs), a nonnegligible part of operation time is spent on global wires with long delays. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC ...

research-article
An overview of the competitive and adversarial approaches to designing dynamic power management strategies

Dynamic power management (DPM) refers to the problem of judicious application of various low-power techniques based on runtime conditions in an embedded system to minimize the total energy consumption. To be effective, often such decisions take into ...

research-article
Gate oxide leakage and delay tradeoffs for dual-toxcircuits

Gate oxide tunneling current (Igate) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (Tox) is below 15 Å. Increasing the value of Tox reduces the leakage at the expense of increased delay, and ...

research-article
Bus encoding for total power reduction using a leakage-aware buffer configuration

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and ...

research-article
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem ...

research-article
Configuration compression for FPGA-based embedded systems

Field programmable gate arrays (FPGAs) are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration ...

research-article
A multiparameter implantable microstimulator SOC

Various implantable microstimulators have been proposed for clinical applications in recent years. Most of the no-battery implanted devices can be powered by a transcutaneous magnetic coupling, which basically utilizes an external transmitter coil to ...

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