IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Research in algorithms for Boolean satisfiability (SAT) and their implementations (Goldberg and Novikov, 2002), (Moskewicz et al., 2001), (Silva and Sakallah, 1999) has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks (ftp:...

The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into ...

The growing market of multimedia applications has required the development of complex application-specified integrated circuits with significant data-path portions. Unfortunately, most high-level synthesis tools and methods cannot automatically ...

Design methods for OR-AND-OR three-level networks are useful for exploiting the flexibility of logic blocks in many complex programmable logic devices. This paper presents T RIMIN, a fast heuristic algorithm for designing OR-AND-OR networks from sum-of-...

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters, taking into account the main effects of deep submicron (DSM) such as velocity saturation and mobility degradation. The relationship between the input and ...

Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial ICs, ...

We deal with problems arising in the coupling of process and device simulators. It is analyzed what kind of data and algorithms such simulations are based on. An overview of existing technology computer-aided design data models is given. A generic ...

The design of analog front-ends of digital telecommunication transceivers requires mixed-signal simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, ...

We present efficient computational methods for scattered point and meshless analysis of electrostatic microelectromechanical systems (MEMS). Electrostatic MEM devices are governed by coupled mechanical and electrostatic energy domains. A self-consistent ...

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with ...

Increasing delay variation due to capacitive and inductive crosstalk has a dramatic impact on deep submicron technologies. It is now impossible to exclude crosstalk from timing analysis. However, timing analysis with crosstalk is a mutual dependence ...

Static timing analysis is instrumental in efficiently verifying a design's temporal behavior to ensure correct functionality at the required frequency. This paper addresses static timing analysis in the presence of crosstalk for circuits containing ...

Recently, the electronic design automation industry has adopted the intellectual property (IP) business model as a dominant system-on-chip development platform. Since copyright fraud has been recognized as the most devastating obstruction to this model, ...

Energy consumption has become a major focus in the design of embedded systems (e.g., mobile computing and wireless communication devices). In particular, a shift of emphasis from hardware-oriented low-energy design techniques to energy-efficient ...