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- Article
A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach
VLSID '16: Proceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)•January 2016, pp 282-287• https://doi.org/10.1109/VLSID.2016.50This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device ...
- Article
Ongoing challenges in automated cyberphysical cross-domain design
ICNC '13: Proceedings of the 2013 International Conference on Computing, Networking and Communications (ICNC)•January 2013, pp 341-347• https://doi.org/10.1109/ICCNC.2013.6504106Cyberphysical systems span domains across mechanical design, controls/signal processing theory, and computational architecture domains. Through an automated holistic design methodology, the interdepen-dence between design domains can be exploited to ...
- Article
2009 MEMOCODE co-design contest
MEMOCODE'09: Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign•July 2009, pp 66-68The 2009 MEMOCODE Co-Design Contest is the third in the series of annual design contests organized by the MEMOCODE Conference. Contestants have one month to create the best performing design solution to a posted design challenge. The contest is open to ...
- Article
Control design for force balance sensors
This paper describes a design methodology for force balance sensors and applies it to the design of a tunneling accelerometer. A controller based on feedback from estimated states is a natural basis for the design. It provides a controller with a rich ...
- Article
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
VLSID '09: Proceedings of the 2009 22nd International Conference on VLSI Design•January 2009, pp 407-412• https://doi.org/10.1109/VLSI.Design.2009.16Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements. In particular, the emerging applications of Micro Electro-Mechanical Systems (MEMS)...
- research-article
Advances in ESL Design
IEEE Design & Test, Volume 25, Issue 6•November 2008, pp 520-526 • https://doi.org/10.1109/MDT.2008.153This is the second of two roundtables on electronic system-level (ESL) design, which recently has been seen as an advance in the EDA community--the latest attempt to improve designer productivity, shorten design time and cost, and improve design ...
- research-article
Synthesizing synchronous elastic flow networks
DATE '08: Proceedings of the conference on Design, automation and test in Europe•March 2008, pp 306-311• https://doi.org/10.1145/1403375.1403449This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behavioral correctness from design performance by allowing any sub-component to ...
- article
Structural integrity: safety in miniature technology
ACM SIGBED Review, Volume 5, Issue 1•January 2008, Article No.: 14, pp 1-2 • https://doi.org/10.1145/1366283.1366297Micro-Electro-Mechanical (MEMS) sensing and actuation devices are poised to reinvent the cyber-physical world by providing environmental connectivity in unprecedented ways. MEMS accelerometers and transducers open the door to sensor networks embedded in ...
- Article
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems•September 2007, pp 95-102• https://doi.org/10.1145/1289881.1289901Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of microns. However, the physical scale of MEMS devices can make controlling them ...
- Article
MEMOCODE 2007 Co-Design Contest
MEMOCODE '07: Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign•May 2007, pp 91-94• https://doi.org/10.1109/MEMCOD.2007.371241New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is distinct from conventional hardware or software design practice. A co-design ...
- Article
A case study of multi-threading in the embedded space
CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems•October 2006, pp 357-367• https://doi.org/10.1145/1176760.1176803The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net processors are tasked with the job of handling a disparate set of interrupt ...
- Article
Extensible control architectures
CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems•October 2006, pp 323-333• https://doi.org/10.1145/1176760.1176800Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true for sequential controllers, where machine complexity can quickly surpass ...
- Article
Layout driven data communication optimization for high level synthesis
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings•March 2006, pp 1185-1190High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow ...
- Article
PyPBS design and methodologies
MEMOCODE '05: Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design•July 2005, pp 55-64• https://doi.org/10.1109/MEMCOD.2005.1487891This paper presents results on processor specification from a specialized high-level finite state machine (FSM) language. The language is an extension and enhancement of earlier production based specification (regular automata) work using modern ...
- Article
Structural search for RTL with predicate learning
DAC '05: Proceedings of the 42nd annual Design Automation Conference•June 2005, pp 451-456• https://doi.org/10.1145/1065579.1065698We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and ...
- Article
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design•May 2005, pp 297-302We present a method that combines interval-arithmetic (IA) and Boolean reasoning with structural hashing for simplifying SAT problems on circuits expressed at the register-transfer level. We demonstrate that simple transformations based on interval-...
- Article
Wirelength optimization by optimal block orientation
ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design•May 2005, pp 64-70Rectangular cells can be flipped in place along either horizontal or vertical axis without changing the area of a layout. During floorplanning, both the location and orientation of cells are determined. However, the complexity of the floorplanning ...
- research-article
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Issue 3•June 2003, pp 461-473 • https://doi.org/10.1109/TVLSI.2003.812310Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to ...
- research-article
Symbolic NFA scheduling of a RISC microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 10, Issue 4•August 2002, pp 429-434 • https://doi.org/10.1109/TVLSI.2002.807349We describe a set of techniques for representing the high-level behavior of a digital subsystem as a collection of nondeterministic finite automata, NFA. Desired behavioral dynamics such as functional dependencies, sequential timing, and sequencing, and ...
- Article
Coping with buffer delay change due to power and ground noise
DAC '02: Proceedings of the 39th annual Design Automation Conference•June 2002, pp 860-865• https://doi.org/10.1145/513918.514131Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the ...