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- ArticleMay 2011
Tool Chain Support with Dynamic Profiling for RISP
ISPA '11: Proceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with ApplicationsPages 155–160https://doi.org/10.1109/ISPA.2011.39This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. The tool chain consists of a profiler, a code map per, and a retargetable compiler. Firstly dynamic profiler ...
- ArticleJune 2004
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
DAC '04: Proceedings of the 41st annual Design Automation ConferencePages 626–658https://doi.org/10.1145/996566.1142985Advances in semiconductor technology permit increasingly complex applications to be realized using programmable systems-on-chips (SOCs). Furthermore, shrinking time-to-market demands, coupled with the need for product versioning through software ...
- articleJune 2004
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 3Pages 626–658https://doi.org/10.1145/1142980.1142985Advances in semiconductor technology permit increasingly complex applications to be realized using programmable systems-on-chips (SOCs). Furthermore, shrinking time-to-market demands, coupled with the need for product versioning through software ...
- ArticleOctober 2002
Efficient architecture/compiler co-exploration for ASIPs
CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systemsPages 27–34https://doi.org/10.1145/581630.581635In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler ...
- articleJuly 2001
Processor modeling and code selection for retargetable compilation
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 6, Issue 3Pages 277–307https://doi.org/10.1145/383251.383252Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve ...
- research-articleApril 2000
MetaCore: an application-specific programmable DSP development system
- Jin-Hyuk Yang,
- Byoung-Woon Kim,
- Sang-Joon Nam,
- Young-Su Kwon,
- Dae-Hyun Lee,
- Jong-Yeol Lee,
- Chan-Soo Hwang,
- Yong-Hoon Lee,
- Seung-Ho Hwang,
- In-Cheol Park,
- Chong-Min Kyung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 8, Issue 2Pages 173–183https://doi.org/10.1109/92.831437This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design ...
- articleJanuary 1998
Retargetable Code Generation Based on Structural Processor Description
Design Automation for Embedded Systems (DAES), Volume 3, Issue 1Pages 75–108https://doi.org/10.1023/A:1008807631619Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW ...
- research-articleMarch 1997
Time-constrained code compaction for DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 5, Issue 1Pages 112–122https://doi.org/10.1109/92.555991This paper addresses instruction-level parallelism in code generation for digital signal processors (DSPs). In the presence of potential parallelism, the task of code generation includes code compaction, which parallelizes primitive processor operations ...