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- research-articleNovember 2011
CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction ...
- ArticleMay 2011
Improved DFT for Testing Power Switches
ETS '11: Proceedings of the 2011 Sixteenth IEEE European Test SymposiumPages 7–12https://doi.org/10.1109/ETS.2011.63Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a ...
- posterAugust 2010
Replication-aware leakage management in chip multiprocessors with private L2 cache
ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and designPages 135–140https://doi.org/10.1145/1840845.1840874Power dissipation has become a critical issue in modern chip multiprocessors (CMPs). Managing the leakage power of their L2 caches is particularly important in realizing low-power CMPs because most CMPs employ large L2 caches to hide the performance gap ...
- ArticleJune 2005
A design platform for 90-nm leakage reduction techniques
- Philippe Royannez,
- Hugh Mair,
- Franck Dahan,
- Mike Wagner,
- Mark Streeter,
- Laurent Bouetel,
- Joel Blasquez,
- H. Clasen,
- G. Semino,
- Julie Dong,
- D. Scott,
- B. Pitts,
- Claudine Raibaut,
- Uming Ko
DAC '05: Proceedings of the 42nd annual Design Automation ConferencePages 549–550https://doi.org/10.1145/1065579.1065722Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide ...