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Fault injection is a common technique to break security algorithms on microcontrollers and other processors. However, it is often unclear which specific effect a physical fault had, for example, which instruction in a firmware binary was changed and how. ...

In order to obtain the secret key, the majority of physical attacks require knowledge of the plaintext or ciphertext, which may be unavailable or cannot be exploited. Blind attacks are introduced to do key recovery in circumstances where the ...

In this study, we suggest two ways to use Statistical Effective Fault Attack (SEFA) in a blind setting that are much less affected by missed faults and noise when measuring power traces, even though they do not use fault injection at the bit level. In ...

With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ...

The authors report the results of a study on the impact of resistive bridging faults on triple modular redundancy (TMR)‐based quasi‐delay‐insensitive (QDI) asynchronous countermeasures, which is used to provide a secure circuit against power analyses. ...

The rate of particle induced soft errors in a processor increases in proportion to the number of bits. This soft error rate (SER) can limit the performance of a system by placing an effective limit on the number of cores, nodes or clusters. The ...

For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit ...

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. ...

The downscaling of technology features has brought the system developers an important design criteria, reliability, into prime consideration. Due to external radiation effects and temperature gradients, the CMOS device is not guaranteed anymore to ...

An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on ...

SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) ...

A new failure model is proposed to simulate familiar failure mode of analog circuit, such as open-circuit and short-circuit mode. With this new model, it becomes much easier and more convenient to carry out fault injection and fault simulation in analog ...

Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting ...

Efficient fault simulation algorithms for combinational circuits are known for decades. However, sequential fault simulation which is frequently used in test and fault tolerance applications remains a very time-consuming task, in particular for larger ...

In this paper we present extensions to the SystemC library and automatable model transformations that enable efficient system-level fault simulation in SystemC. The method is based on extended data types which represent variables or signals as lists of ...

Field Programmable Gate Arrays (FPGAs) are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this ...

High-availability is a critical feature to database customers; having a way to measure and characterize availability is important for guiding system development and evaluating different HA technologies. This paper describes extensions to the TPC-E ...

The following topics are dealt with: built-in self-test; automatic test generation; industrial experience; process control; process variation; fault modeling; fault simulation; HDL-based IC design; thermal-aware design; low-power design; mixed-signal ...

Verification of Linux kernel modules and especially device drivers is a critically important task. However, due to the special nature of the kernel operation, it is very challenging to perform runtime analysis of particular kernel modules of interest ...

Although analog circuit simulation tool like Saber software are numerous, however, it is lack of software which can simulate analog circuits affected by fault modes. Research in the fields of analog circuit fault simulation has not achieved the same ...

In scan-based testing environments, identifying the scan chain failures can be of significant help in guiding the failure analysis process for yield improvement. In this paper, we propose an efficient scan chain diagnosis method using a symbolic fault ...