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Front cover
The following topics are dealt with: built-in self-test; automatic test generation; industrial experience; process control; process variation; fault modeling; fault simulation; HDL-based IC design; thermal-aware design; low-power design; mixed-signal ...
Analysis of SEU parameters for the study of SRAM cells reliability under radiation
A simplified RC circuit is used to simulate the effects of ionizing particles in a 90nm SRAM. The main characteristic of the memory cell bit flip are discussed and compared for characteristic parameters. The effect of the surrounded circuit on the ...
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
Three-dimensional integration is a key technology for systems whose performance / power requirements cannot be achieved by traditional silicon technologies. Testing is one of the major challenges of 3D integration. This paper proposes a configurable ...
Testing in an agile product development environment: An industry experience report
Product development nowadays requires great focus on time to market, as well as in quality, in order to meet customer expectations. Several agile methods and methodologies have been proposed to tackle the early release of software products and meet ...
Functional test generation for the pLRU replacement mechanism of embedded cache memories
Testing cache memories is a challenging task, especially when targeting complex and high-frequency devices such as modern processors. While the memory array in a cache is usually tested exploiting BIST circuits that implement March-based solutions, ...
Communication fault injection for multi-protocol Java applications testing
Network applications with high dependability requirements must be carefully tested under communication faults to enhance confidence in proper behavior. Fault injection is very useful for these tests. When the applications use more than one protocol, ...
Formally verifying an RTOS scheduling monitor IP core in embedded systems
The implementation of complex, high-performance functionalities in nano-CMOS technologies faces significant design and test challenges related to the need of adopting robust and efficient system validation methodologies. This aspect is particularly true ...
Reliability enhancement via Sleep Transistors
CMOS is still the predominating technology for digital designs with no identifiable concurrence in the near future. Driving forces of this leadership are the high miniaturization capability and the reliability of CMOS. The latter, though, is decreasing ...
An improved OBT strategy for untuned continuous-time analog filters
This paper presents an enhanced Oscillation Based Test (OBT) scheme that performs a relative comparison between two oscillation frequencies, eliminating the need of a fixed reference and allowing in this way the application of the OBT technique to non ...
A TLM-based approach to functional verification of hardware components at different abstraction levels
Verification has long been recognized as an integral part of the hardware design process. When designing a system, engineers usually use various design representations and concretize them step by step up to a physical layout. At the beginning of the ...
A fault-tolerant service discovery protocol for emergency search and rescue missions
In service discovery protocols for mobile ad hoc networks (Manets) assisting emergency search and rescue missions, a key problem is to keep the system operating despite the existence of faults. In this paper, we propose a fault-tolerant service ...
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench
In this paper, we propose a technique for the detection of neutrons in atmospheric environment developed in the framework of HAMLET project. This technique relies on the sensitivity of SRAM cells to particle radiation. In particular, we introduce a ...
Methodology and platform for fault co-emulation
A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their ...
Impact of RF-based fault injection in Pierce-type crystal oscillators under EMC standard tests in microcontrollers
Crystal oscillators are usually implemented using Pierce's configuration due to its high stability, small amount of components, and easy adjustment. With technology development and device shrinking, modern microcontroller embedded oscillators include ...
Test and calibration of MEMS convective accelerometers with a fully electrical setup
MEMS devices are expected to be used in a growing number of high-volume and low-cost applications. However because they typically requires the application of physical test stimuli to verify their specifications, test and calibration costs are actually a ...
Behavioral-level thermal- and aging-estimation flow
In recent transistor technologies design metrics highly interdepend on each other and cannot be regarded isolated. For example temperature analysis requires detailed knowledge of the power consumption and leakage currents exponentially depend on the ...
On the functional test of MESI controllers
This paper proposes a method to identify a functional sequence able to test the circuitry implementing the MESI protocol in a multi-processor or multi-core system. The method is purely functional and does not require any knowledge about the real ...
Error-resilient design of branch predictors for effective yield improvement
Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its ...
Test power reduction via deterministic alignment of stimulus and response bits
Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering ...
IC immunity modeling process validation using on-chip measurements
Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC ...
Scan chain configuration method for broadcast decompressor architecture
The high test data volume and long test application time are two major concerns for testing scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. The broadcast rate is a major ...
Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors
There is a large set of software-based techniques that can be used to detect transient faults. This paper presents a detailed analysis of the efficiency of dataflow software-based techniques to detect SEU and SET in microprocessors. A set of well-known ...
Testing linear and non-linear analog circuits using moment generating functions
Circuit under test (CUT) is treated as a transformation on the probability density function of its input excitation, which is, a continuous random variable (RV) of gaussian probability distribution. Probability moments of the output, which is now the ...
Robustness with respect to SEUs of a self-converging algorithm
Self-convergence is a property of distributed systems, allowing a system, when it was perturbed or badly initialised, to recover a correct operation in a finite number of calculation steps. In this paper is explored the intrinsic robustness of a self ...
Modular and adaptative test-bed for infrared photodetectors
Nowadays, the detection in the infrared band (IR) has shown great importance in several areas such as skin illnesses detection, remote sensor and in different military devices. The responsible for such detection is, basically, photodetector arrays (FPA) ...
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study
- M. Portela-Garcia,
- A. Lindoso,
- L. Entrena,
- M. Garcia-Valderas,
- C. Lopez-Ongil,
- B. Pianta,
- L. B. Poehls,
- F. Vargas
Microprocessor-based system's robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection ...
An approach for clustering test data
The existing test techniques and criteria are considered complementary because they can reveal different kinds of faults and test specific aspects of the program. The functional criteria, such as Category Partition, are difficult to be automated, and ...