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- research-articleSeptember 2020Honorable Mention
Fast ECO Leakage Optimization Using Graph Convolutional Network
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSIPages 187–192https://doi.org/10.1145/3386263.3406916At the very late design stage, engineering change order (ECO) leakage optimization is often performed to swap some cells for the ones with lower leakage, e.g. the cells with higher threshold voltage (Vth) or with longer gate length. It is very effective ...
- research-articleJune 2020
Engineering change order for combinational and sequential design rectification
Engineering change order (ECO) becomes a crucial element in VLSI design flow to rectify function or fix non-functional requirements in late design stages. Even though commercial ECO solutions are available, ECO remains much room for improvement due to ...
- research-articleApril 2019
Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions
ISPD '19: Proceedings of the 2019 International Symposium on Physical DesignPages 109–116https://doi.org/10.1145/3299902.3311069We first present historical view on the techniques for two-level and multi-level logic optimizations, and discuss the practical issues with respect to them. Then the techniques for sequential optimizations are briefly reviewed. Based on them, a new ...
- research-articleNovember 2017
ICCAD-2017 CAD contest in resource-aware patch generation
With a functional Engineering Change Order (ECO) problem, the quality of patch plays an important role in the performance of the patched circuit. In this contest, contestants need to generate patch functions that will make two circuits equivalent, while ...
- research-articleJune 2016
Design partitioning for large-scale equivalence checking and functional correction
DAC '16: Proceedings of the 53rd Annual Design Automation ConferenceArticle No.: 23, Pages 1–6https://doi.org/10.1145/2897937.2898004Equivalence checking and functional correction are important steps ensuring design correctness. Direct verification of large industrial designs is challenging and often requires a divide-and-conquer approach. The 2015 CAD Contest at ICCAD poses the ...
- tutorialNovember 2015
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignPages 916–920Equivalence checking (EC) and functional Engineering Change Order (ECO) on large-scale designs becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in how to partition the large-scale problems into ...
- tutorialNovember 2015
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignPages 890–894To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a ...
- posterFebruary 2015
On Implementation of LUT with Large Numbers of Inputs (Abstract Only)
FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 277https://doi.org/10.1145/2684746.2689107A LUT is implemented with a set of flipflops which are connected to a series of multiplexers, or alternatively with a small memory, and needs exponentially many storage elements with respect to the numbers of inputs. Due to this FPGA uses LUTs having ...
- research-articleMarch 2013
PushPull: short path padding for timing error resilient circuits
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical DesignPages 50–57https://doi.org/10.1145/2451916.2451928Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the ...
- research-articleMarch 2013
Intuitive ECO synthesis for high performance circuits
In the IC industry, chip design cycles are becoming more compressed, while designs themselves are growing in complexity. These trends necessitate efficient methods to handle late-stage engineering change orders (ECOs) to the functional specification, ...
- research-articleNovember 2012
Opening: introduction to CAD contest at ICCAD 2012
ICCAD '12: Proceedings of the International Conference on Computer-Aided DesignPage 341https://doi.org/10.1145/2429384.2429454Contests and their benchmarks have become an important driving force to push our EDA domain forward in different areas lately, such as ISPD, TAU, DAC contests. To encourage better research development on timely and practical EDA problems across all ...
- research-articleJune 2012
Timing ECO optimization using metal-configurable gate-array spare cells
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 802–807https://doi.org/10.1145/2228360.2228505Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare ...
- research-articleJune 2011
Interpolation-based incremental ECO synthesis for multi-error logic rectification
DAC '11: Proceedings of the 48th Design Automation ConferencePages 146–151https://doi.org/10.1145/2024724.2024758To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle ...
- research-articleJune 2011
Simultaneous functional and timing ECO
DAC '11: Proceedings of the 48th Design Automation ConferencePages 140–145https://doi.org/10.1145/2024724.2024757Metal-only ECO is prevalent at design houses to perform incremental design changes to resolve last found functional and/or timing failures. However, it is hard to perform mixed functional and timing changes manually. Prior endeavors focus on functional ...
- articleSeptember 2010
ECO-aware obstacle-avoiding routing tree algorithm
This study formulates a novel routing problem of engineering change order- (ECO for short) aware Steiner minimal tree with obstacles and solves it by a multiple-stage approach, including partitioning, analysis distribution of spare cells, virtual node ...
- ArticleNovember 2003
Stable Multiway Circuit Partitioning for ECO
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided designPage 718We propose a new stable multiway partitioning algorithm,where stability is defined as an additional quality of a partitioningsolution. The stability of a partitioning algorithm isan important criterion for a partitioning based placement toachieve timing ...