ICCAD

State Restoration Ratio (SRR) has been the de facto standard for evaluating quality of signals selected for post-silicon tracing and debug. Given a set S of selected signals, SRR measures the fraction of (gate-level) design states that can be inferred ...

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a ...

Low overhead error-resiliency techniques such as RAZOR [1] and algorithmic noise-tolerance (ANT) [2] have proven effective in reducing energy consumption. ANT has been shown to be particularly effective for signal processing and machine learning ...

The replacement of DRAM with non-volatile memory relies on solutions to resolve the wear leveling and slow write problems. Different from the past work in compiler-assisted optimization or joint DRAM-PCM management strategies, we explore a light-...

The growing popularity of embedded Multi-Media Controllers (eMMCs) presents a unique opportunity to design commodity grade solid-state drives products. This work addresses the essential design issues of such drives and introduces a light-weight FTL ...

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is a major concern.

We introduce the first cross-layer ...

Self-awareness has a long history in biology, psychology, medicine, and more recently in engineering and computing, where self-aware features are used to enable adaptivity to improve a system's functional value, performance and robustness. With complex ...

Run-time solutions based on real-time monitoring and adaptation are required for resilience in nanoscale integrated circuits as design-time solutions and guard bands are no longer sufficient. Bias Temperature Instability (BTI)-induced transistor aging, ...

Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions). As device bandwidths expand, it becomes ...

Formal methods advanced to an important core technique in Computer-Aided Design (CAD). At the same time, researchers and engineers also started the investigation of so-called emerging technologies such as reversible computation, quantum computation, or ...

Code motion and speculations are usually exploited in the High Level Synthesis of control dominated applications to improve the performances of the synthesized designs. Selecting the transformations to be applied is not a trivial task: their effects can ...

Modern high-level synthesis (HLS) tools commonly employ pipelining to achieve efficient loop acceleration by overlapping the execution of successive loop iterations. However, existing HLS techniques provide inadequate support for pipelining irregular ...

Current nanoscale designs are highly interconnect dominated, taking about 70% of the chip area. Interconnects also consume significant dynamic power, and about 60% of signal delays. It is thus important to be able to synthesize much lower interconnect-...

In this paper, we take a fresh look at a well-known NP-complete problem---the exact minimization of incompletely specified Mealy machines. Most existing exact techniques in this area are based on the enumeration of sets of compatible states, and the ...

We show how to incorporate global static timing constraints into global routing. Our approach is based on the min-max resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a ...

As VLSI technology scales to deep submicron and beyond, interconnect delay greatly limits the circuit performance. The traditional 2D global routing and subsequent net by net assignment of available empty tracks on various layers lacks a global view for ...

FPGA routing is a time-consuming step in the EDA design flow. In this paper we present a coarse-grained recursive partitioning approach to exploit parallelism. The basic idea is to partition the nets into three subsets, where the first subset and the ...

Clock tree and clock mesh are two extreme structures of clock networks. Clock tree is good at saving clock wires and power, but is vulnerable to clock skew variation. On the other hand, clock mesh is good at mitigating clock skew variation, but spends ...

Counterfeit Integrated Circuits (IC) can be very harmful to the security and reliability of critical applications. Physical Unclonable Functions (PUF) have been proposed as a mechanism for uniquely identifying ICs and thus reducing the prevalence of ...

Resistance switching memories have emerged as a promising solution for low power and high density non-volatile storage. Unique electronic properties of resistive RAMs (and memristors) have attracted not only memory applications, but other applications ...

The counterfeiting and recycled integrated circuits (ICs) has become a major security threat for commercial and military systems. In addition to the huge economic impacts, they post significant security and safety threats on those systems. In this paper,...

Physical Unclonable Functions (PUFs) are cryptographic primitives that can be used to generate volatile secret keys for cryptographic operations and enable low-cost authentication of integrated circuits. Existing PUF designs mainly exploit variation ...

Circuit and design techniques for fine-grain power management in manycore System-on-Chip (SoC) are presented. Recent advances in dynamic platform control techniques to enable (1) independent voltage-frequency domains, (2) dynamic power budget allocation ...

During the last decade, we have witnessed a major transition from computation- to communication-centric design of integrated circuits and systems. In particular, the network-on-chip (NoC) approach has emerged as the major design paradigm for multicore ...

The continuous increase in integration densities contributed to a shift from Dennard's scaling to a parallelization era of multi-/many-core chips. However, for multicores to rapidly percolate the application domain from consumer multimedia to high-end ...

This paper introduces the power-density and temperature induced issues in the modern on-chip systems. In particular, the emerging Dark Silicon problem is discussed along with critical research challenges. Afterwards, an overview of key research efforts ...

Stochastic computing (SC) acts on data encoded by bit-streams, and is an attractive, low-cost and error-tolerant alternative to conventional binary circuits in some important applications such as image processing and communications. We study the use of ...

Cellular neural networks (CNNs) are a powerful analog architecture that can outperform traditional von Neumann architecture for spatio-temporal information processing applications, e.g., image processing and speech recognition. Much existing work ...

The cross-point array architecture with resistive synaptic devices has been proposed for on-chip implementation of weighted sum and weight update in the training process of learning algorithms. However, the non-ideal properties of the synaptic devices ...

Proliferation of internet-of-things (IoT) will lead to scenarios where humans will interact with and control a variety of networked devices including sensors and actuators. Wearable brain-machine interfaces (BMI) can be a key enabler of this interaction ...