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- review-articleOctober 2024
A synoptic review of nanoscale vacuum channel transistor: Fabrication to electrical performance
AbstractThe vacuum channel transistor has emerged as a promising candidate for next-generation technology due to its intriguing features compared to the conventional field effect transistor. Nanoscale vacuum channel transistors have a particular ...
Highlights- Emerging Technology: Vacuum channel transistors are a promising candidate for next-generation technology, offering advantages such as vacuum-like ballistic transport, radiation insensitivity, and nanoscale dimensions.
- Historical ...
- research-articleNovember 2024
Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation ConferenceArticle No.: 132, Pages 1–6https://doi.org/10.1145/3649329.3655925Design-Technology Co-Optimization (DTCO) can be significantly accelerated by employing Neural Compact Models (NCMs). However, the effective deployment of NCMs requires a substantial amount of training data for accurate device modeling. This paper ...
- research-articleMay 2024
Simulation and machine learning based analytical study of single electron transistor (SET)
Journal of Computational Electronics (SPJCE), Volume 23, Issue 4Pages 728–739https://doi.org/10.1007/s10825-024-02175-4AbstractIn recent years, the requirement for greater scalability of transistor technology for the continuation of Moore’s law has led researchers toward the investigations of several innovative advanced semiconductor device as potentially superior ...
- research-articleMarch 2024
Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories
AbstractIn this study, we proposed a novel multi-bit content addressable memory (MCAM) cell based on one single double-gated ferroelectric-gate FET (DG-FeFET). Baseline DG-FeFET has been modeled, and the parameters are calibrated with experimental ...
Highlights- Proposed a novel multi-bit content addressable memory (MCAM) cell based on one single double-gated ferroelectric-gate FET.
- Corresponding writing and searching operations are investigated in detail by the TCAD Sentaurus model.
- Boost ...
- research-articleDecember 2023
Design and implementation of high-performance 20-T hybrid full adder circuit
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 119, Issue 1Pages 97–110https://doi.org/10.1007/s10470-023-02219-yAbstractA new high-performance exclusive OR/exclusive NOR (XOR/XNOR) architecture with ten transistors is proposed in this work. Our research focused on implementing a hybrid exclusive OR/exclusive NOR circuit to achieve high performance, good driving ...
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- research-articleFebruary 2024
Simulation study on quantum dot formation of double-qubit-Si-MOS device
AbstractSilicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and ...
- research-articleFebruary 2024
Analytical modeling and numerical simulation of graded JAM Split Gate-All-Around (GJAM-SGAA) Bio-FET for label free Avian Influenza antibody and DNA detection
AbstractThis manuscript presents the analytical model of a novel biosensor called Graded JAM Split Gate-All-Around (GJAM-SGAA) Bio-FET for the detection of Avian Influenza antibody and DNA. The GJAM-SGAA Bio-FET utilizes a silicon Gate-All-Around FET ...
- research-articleNovember 2023
On-chip ESD Protection Design Methodologies by CAD Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 1Article No.: 4, Pages 1–41https://doi.org/10.1145/3593808Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs). On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional ...
- research-articleAugust 2023
Ge/Si interfaced label free nanowire BIOFET for biomolecules detection - analytical analysis
AbstractThis paper comprehensively investigates a dielectric modulated Ge/Si interfaced label free nanowire BIOFET for biomolecules detection. The main highlight of this work is the structural novelty in nanowire BIOFET which is integrated ...
- research-articleJuly 2023
Low-frequency noise performance of a molybdenum ditelluride double-gate MOSFET
Journal of Computational Electronics (SPJCE), Volume 22, Issue 5Pages 1433–1442https://doi.org/10.1007/s10825-023-02074-0AbstractThis work investigates the low-frequency noise performance of a 2H-type monolayer/bilayer molybdenum ditelluride (MoTe2) double-gate MOSFET. A hybrid simulation technique involving both QuantumWise ATK and Sentaurus TCAD tools has been used to ...
- research-articleJuly 2023
Performance comparison of vertically stacked nanosheet CFET and standard CMOS without and with parasitic channels
AbstractThe threshold voltage regulation and the effect of parasitic channels are important issues in CFET. In this paper, the characteristics of the complementary field-effect transistor (CFET) were simulated based on a self-aligned ...
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Highlights- The threshold voltage of pFET is adjusted to match nFET by the work function metal, which can obtain a good VTC. (In reality, usually different WF metals are ...
- research-articleJuly 2023
A deterministic Wigner transport equation solver with infinite correlation length
Journal of Computational Electronics (SPJCE), Volume 22, Issue 5Pages 1377–1395https://doi.org/10.1007/s10825-023-02079-9AbstractWe propose a new formulation of the Wigner transport equation (WTE) with infinite correlation length. Since the maximum correlation length is not limited to a finite value, there is no uncertainty in the simulation results owing to the finite ...
- research-articleFebruary 2023
Numerical modeling of a dielectric modulated surrounding-triple-gate germanium-source MOSFET (DM-STGGS-MOSFET)-based biosensor
Journal of Computational Electronics (SPJCE), Volume 22, Issue 2Pages 742–759https://doi.org/10.1007/s10825-023-02008-wAbstractThis paper presents for the first time an analytical model of a dielectric modulated surrounding-triple-gate MOSFET with a germanium source-based biosensor, which shows excellent improvement in sensitivity when compared to a silicon source. The ...
- research-articleNovember 2022
Impact on performance of dual stack hetero- gated dielectric modulated TFET biosensor due to Si1-xGex pocket variation
AbstractIn this work, the performance evaluation of a dual stack hetero-gated pocket modulated tunnel FET (DSHGPM-TFET) based biosensor is presented. In the proposed device, cavity is formed by etching a portion of gate metal on both side of ...
- research-articleAugust 2022
ASAP5: A predictive PDK for the 5 nm node
AbstractWe present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the ...
- research-articleMay 2022
Parametric investigation and trap sensitivity of n-p-n double gate TFETs
Computers and Electrical Engineering (CENG), Volume 100, Issue Chttps://doi.org/10.1016/j.compeleceng.2022.107930Highlights- Gate-on-drain length in npn TFET is similar to gate-drain underlap in pin TFET.
This article reports an architecture of a silicon-on-insulator (SOI) tunnel field effect transistor (TFET) possessing an n-p-n body, where the two p-n junctions serve as the primary tunneling sites. The p-type source region is elevated ...
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- research-articleFebruary 2022
Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle
Journal of Computational Electronics (SPJCE), Volume 21, Issue 1Pages 181–190https://doi.org/10.1007/s10825-021-01819-zAbstractWe use the superposition method to model the electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunneling field-effect transistor (TFET). The heterojunction is formed from Ge/Si material in the source/channel, ...
- research-articleAugust 2021
LET-dependent model of single-event effects in MOSFETs
Journal of Computational Electronics (SPJCE), Volume 20, Issue 4Pages 1496–1503https://doi.org/10.1007/s10825-021-01713-8AbstractIn this paper, we simulate the electrical characteristics of the n-type metal-oxide-semiconductor (NMOS) transistor in a 65-nm complementary metal-oxide-semiconductor (CMOS) inverter under the actions of heavy ions with different linear energy ...
- research-articleJune 2021
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects
- Thiago Copetti,
- Guilherme Cardoso Medeiros,
- Mottaqiallah Taouil,
- Said Hamdioui,
- Letícia Bolzani Poehls,
- Tiago Balen
Journal of Electronic Testing: Theory and Applications (JELT), Volume 37, Issue 3Pages 383–394https://doi.org/10.1007/s10836-021-05949-xAbstractFin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating ...