RTNS

We study the effect of store buffers on the timing predictability of processor pipelines. We show that the concurrency between the load unit and the store buffer to access the memory bus is an obstacle to timing predictability, even in simple scalar in-...

Parametric Worst-Case Execution Time (WCET) is a static analysis that computes a WCET formula that depends on various parameters. The formula can be used off-line for fast parameter space exploration, and on-line for adaptive scheduling.

In this work, ...

Caches are used to bridge the gap between main memory and the significantly faster processor cores. In multi-core architectures, the last-level cache is often shared between cores. However, sharing a cache causes inter-core interference to emerge. ...

Thermal management is a crucial aspect of the design and operation of safety-critical multi-core architectures, as their high power density can cause significant heat generation and risk of thermal overload. If not properly managed, thermal overload can ...

Soft real-time multiprocessor systems frequently adopt the G-EDF (Global-Earliest Deadline First) scheduling policy as it is lightweight and it guarantees bounded tardiness. Much effort has been spent in literature to provide efficiently computable ...

We identify the budget and the utilization of an aperiodic server as vital attributes that affect its performance. Based on this observation, we formulate an optimization problem in which we are given a minimum budget for multiple servers running at ...

The elastic task model was proposed to allow for the accurate modeling of recurrent real-time workloads that are somewhat flexible with regards to the frequency at which they must be invoked. This is achieved by specifying a range of values for each ...

Fully autonomous driving applications rely on a complete knowledge of their operational environment to ensure safety while maintaining efficient driving. However, in scenarios with close visual restrictions, such as urban traffic, the lack of sensor ...

Network-on-Chips (NoCs) have proven to be a good alternative to traditional bus-based communication architectures to interconnect all programming elements (PEs) in modern Multiprocessor Systems- on-Chips (MPSoC). Wormhole switching with Virtual-Channels ...

LoRaWAN is a wide area network solution for large-area sensor networks; long range (LoRa) transmissions can be achieved, with low power transmissions, but only for very low bandwidth. One of the main challenges is the lack of guarantees in LoRaWAN, ...

Resource reservation is a fundamental mechanism for ensuring quality of service in time-sensitive networks, which can be decentralized by using reservation protocols. In the Ethernet technology Time-Sensitive Networking, this has been proposed in ...

The GNU/Linux operating system (OS) is becoming more commonly used in real-time systems and has been modified with specific updates to provide faster and bounded response times as well as with fixed- and dynamic-priority real-time scheduling ...

Connected embedded systems and cyber-physical systems exhibit larger attack surface than isolated ones. Control-flow integrity (CFI) is a set of techniques to prevent attackers from redirecting program control-flow and performing arbitrary computation, ...

This paper addresses the problem of real-time classification-based machine perception, exemplified by a mobile autonomous system that must continually check that a designated area ahead is free of hazards. Such hazards must be identified within a ...

Many safety-critical systems are required to have their correctness validated prior to deployment. Such validation is typically performed using models of the run-time behaviour that the system is expected to exhibit and experience during run-time. ...

Multicore architectures provide the increased performance required by modern embedded real-time systems. Most platforms exhibit a non-uniform memory access (NUMA). In NUMA, memory banks with different access time can be explicitly addressed. Such an ...

Scheduling of tasks on multi- and many-cores benefits significantly from the efficient use of caches. Most previous approaches use the static analysis of software in the context of the processing hardware to derive fixed allocations of software to the ...

Hardware resources found in modern processor architecture, such as the memory hierarchy, can improve the performance of a task by anticipating its needs based on its execution history and behaviour. Interleaved jobs, belonging to other tasks with ...

Cache partitioning is a technique to reduce interference among tasks accessing the shared caches. To make this technique effective, cache segments must be given to the tasks that can benefit most from having their data and instructions cached for ...

The Logical Execution Time paradigm is a promising approach for achieving time-deterministic communication on multi-core CPUs. Task scheduling under this paradigm is a variant of the Multi-Row Facility Layout Problem, which is known to be NP-hard. In ...

Software applications in automotive systems are comprised of communicating real-time tasks, described by cause-effect chains. To guarantee functional correctness, it is mandatory to verify end-to-end timing latencies of the cause-effect chains. The ...