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Localization microscopy enhances the resolution of fluorescence light microscopy by about an order of magnitude. Single fluorescent molecules act as switchable markers. Their detected signals can be fitted with a two-dimensional Gaussian distribution ...

Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware ...

Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip ...

The Sinusoidal Pulse Width Modulation (SPWM) principle is widely used in power electronic DC/AC converters (inverters) in energy conversion and motor control applications. The digital SPWM generation unit implementations have dominated over their ...

Thanks to their inherent regularity and reconfigurability, FPGAs offer an ideal structure to manage process variability. Recent works from the literature have addressed the process characterization problem for FPGAs: proposed approaches rely on process ...

As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy ...

The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the ...

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In ...

Formal verification is one of the most important applications of the satisfiability (SAT) problem. WSAT and its variants are one of the best performing stochastic local search algorithms. In this paper, we propose an FPGA solver for SAT-encoded ...

We present a full-parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector ...

In the clinical applications, medical image registrations on the images taken from different times and/or through different modalities are needed in order to have an objective clinical assessment of the patient. Viscous fluid registration is a powerful ...

We explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips ...

XDLCoreGen is described, a module generator framework which directly generates placed and routed hard macros in XDL. XDLCoreGen is intended to be used in a rapid prototyping flow such as HM Flow, which achieves short FPGA implementation times by ...

The dynamic partial reconfiguration of FPGAs is a method which modifies parts of FPGA configuration memory at run-time. The hardware resources and time overhead needed to perform a partial reconfiguration (PR) can significantly impact overall system ...

Many FPGA based Network-on-Chip (NoC) and directly connected clusters use routers implemented in the FPGA fabric. Existing projects have optimized the routers for low resource utilization, low latency, and high bandwidth, often at the cost of ...

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, ...

Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a modular solution to the complex system-wide communication issues. The switches are the ...

This paper presents the world's fastest complex event processing system, designed to process a large number of events on FPGAs. Unlike conventional SQL-based approaches, our approach features logic automation constructed with a new C-based event ...

In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA ...

The Well Equidistributed Long-period Linear (WELL) algorithm is proven to have better characteristics than the Mersenne Twister (MT), one of the most widely used long-period pseudo-random number generators (PRNGs). In this paper, we propose a hardware ...

Field Programmable Gate Arrays (FPGAs) are now considered to be one of the preferred computing platforms for high performance computing applications, such as Monte Carlo simulations, due to their large computational power and low power consumption. ...

We propose a universal method to automatically generate both data paths and the appropriate application-specific speculation-support logic from high-level C-language descriptions. Our approach aims to be lightweight by extending efficient statically-...

We introduce CAPH, a new domain-specific language (DSL) suited to the implementation of stream-processing applications on field programmable gate arrays (FPGA). \caph relies upon the actor/dataflow model of computation. Applications are described as ...