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Until recently, data was gathered for well-defined objectives such as auditing, forensics, reporting and line-ofbusiness operations; now, exploratory and predictive analysis is becoming ubiquitous, and the default increasingly is to capture and store ...

Many methods are available to detect silent errors in high-performance computing (HPC) applications. Each comes with a given cost and recall (fraction of all errors that are actually detected). The main contribution of this paper is to characterize the ...

Performance scaling is now synonymous with scaling the number of cores. One of the consequences of this shift is the increasing difficulty of designing processors with predictable and controllable performance. To address this challenge this paper ...

In this paper, we propose an approach of application taxonomy from a perspective of algorithmic commonality. The taxonomy exploits algorithm-inherent characterization to imply a categorization of domain-specific architecture in the initial phase of ...

In the realm of desktop and server class processors, the prevailing trend is to use out-of-order superscalar cores that exploit the hidden instruction-level parallelism in a program. In superscalar designs, the performance (as measured by the IPC, ...

Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Prior work on GPC synthesis using FPGAs has focused on utilizing the fast carry chain and mapping the logic onto LUTs. This mapping is not optimal in ...

Modern solid state disk (SSD) has a buffer (SDRAM), which is used to store commonly used data and map in the near future. How to efficient management of this buffer is an important things of improving performance of SSD. Flash read and write speed have ...

Recent studies have shown the potential of task-based programming paradigms for implementing robust, scalable sparse direct solvers for modern computing platforms. Yet, designing task flows that efficiently exploit heterogeneous architectures remains ...

Sparse matrix vector multiplication (SpMV) is an important linear algebra primitive. Recent research has focused on improving the performance of SpMV on GPUs when using compressed sparse row (CSR), the most frequently used matrix storage format on CPUs. ...

As the computational power of high performance computing (HPC) systems continues to increase by using a huge number of CPU cores or specialized processing units, extreme-scale applications are increasingly prone to faults. Consequently, the HPC ...

Modern GPUs (Graphics Processing Units) offer very high computing power at relatively low cost. Nevertheless, designing efficient algorithms for the GPUs usually requires additional time and effort, even for experienced programmers. On the other hand, ...

In this work, we present a stable parallel algorithm based on WZ factorization for solving diagonally dominant tridiagonal linear system of algebraic equations, using divide and conquer approach. Existence results are given and the backward error ...

Matching is a fundamental graph problem with numerous applications in science and engineering. While algorithms for computing optimal matchings are difficult to parallelize, approximation algorithms on the other hand generally compute high quality ...

Achievable networking performance of applications in a supercomputer depends on the exact combination of the communication patterns of the applications and the routing algorithms used by the supercomputer. In order to achieve the highest networking ...

A vast majority of legacy runtime systems and middleware prevalent in cluster and supercomputing environments are static in nature. Due to the rising scale and complexity of high-performance computing systems, the static nature of systems software would ...

In this work, we study the performance benefits of using asynchronous data transfers in OpenCL programs executing on media processors. Asynchronous data transfers are typically implemented by use of Direct Memory Access (DMA) engines that can be ...

This article presents an innovative runtime support for speculative parallel processing of discrete event simulation models on multi-core architectures, which exploits Hardware-Transactional-Memory (HTM) facilities for the purpose of state ...

Increased performance demand of modern applications has resulted in large memory modules and higher performance processors in computing systems. Power consumption becomes an important aspect when these resources go underutilized in a running system, ...

POWER8 is a new generation of POWER processor capable of 8-way simultaneous multi-threading per core. High-performance computing capabilities, such as high amount of instruction-level and thread level parallelism, are integrated with a deep memory ...

Compiler technology has enabled the software advances of the last sixty years. It has given us machine-independent programming and improved productivity by automatically handling a number of issues, such as instruction selection and register allocation. ...

Principal component analysis (PCA) is a widely used mathematical technique for dimensionality reduction that works by identifying a smaller number of linearly uncorrelated variables (principal components) to explain the variation found in a data set. ...