research-article

Ferroelectric Transistor based Non-Volatile Flip-Flop

Authors:

Sumitha George,

Ahmedullah Aziz,

Vijaykrishnan Narayanan,

Sumeet K. GuptaAuthors Info & Claims

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Pages 10 - 15

https://doi.org/10.1145/2934583.2934603

Published: 08 August 2016 Publication History

Abstract

We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40%--50% smaller backup delay, 27%--40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.

References

[1]

T. Jhaveri, et al, "Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings," IEEE Trans. Computer-Aided Des Int. Circ. and Sys,vol. 29, no. 4, pp. 509--527, 2010.

Digital Library

[2]

B. Rajamohanan et al., "0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET," IEEE Electron Device Letters, vol. 36, no. 1, pp. 20--22, Jan. 2015.

[3]

A. B. Andrew et al, "Growth and transport properties of complementary germanium nanowire field-effect transistors", Appl. Phys. Lett., 84, 4176 (2004).

[4]

S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices", Nano Lett., 2008, 8 (2), pp 405--410.

[5]

A. Khan, et al, "Experimental evidence of ferroelectricnegative capacitance in nanoscale heterostructures", Appl.Phys. Lett. 99, 113501 (2011).

[6]

S. L. Miller and P. J. McWhorter, "Physics of the ferroelectric nonvolatile memory field effect transistor", J. Appl. Phys., 72, 5999 (1992).

[7]

S. Henzler et al., "Dynamic state-retention flip-flop for finegrained power gating with small design and power overhead," IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1654--1661, July 2006.

[8]

Y. Liu et al, "Ambient energy harvesting nonvolatile processors: from circuit to system", Design Automation Conference, 2015.

Digital Library

[9]

K. Ma et al., "Architecture exploration for ambient energy harvesting nonvolatile processors," High Performance Computer Architecture, 2015, pp. 526--537.

[10]

K.-W Kwon et al, "SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture", IEEE Electron Device Letters, vol. 35, no. 4, 2014. pp: 488--490.

[11]

Y. Wang et al., "A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops," ESSCIRC, 2012, pp. 149--152.

[12]

H. Kimura et al, "Highly Reliable Non-Volatile Logic Circuit Technology and Its Application", Int. Symp.Mult.-Valued Logic, 2013, pp: 212--218.

Digital Library

[13]

A. I. Khan, et al, "Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation," Int. Electron Devices Meeting, 2011, pp. 11.3.1--11.3.4

[14]

T. K. Song, "Landau-Khalatnikov Simulations for Ferroelectric Switching in Ferroelectric Random Access Memory Application", Journal of the Korean Physical Society, vol. 46, no. 1, pp. 5~9, 2005.

[15]

https://www.mosis.com/files/scmos/scmos.pdf

[16]

J. Li, et al "Ultrafast polarization switching in thin-film ferroelectrics", App. Phys Lett, vol. 84, no. 7, pp: 1174--1176, Feb 2004.

[17]

A. Aziz, et al, "Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors," IEEE Electron Device Letters, vol. 37, no. 6, pp. 805--808, June 2016.

[18]

http://ptm.asu.edu

Cited By

Leblanc CSong SJariwala D(2024)2D Ferroelectrics and ferroelectrics with 2D: Materials and device prospectsCurrent Opinion in Solid State and Materials Science10.1016/j.cossms.2024.10117832(101178)Online publication date: Sep-2024
https://doi.org/10.1016/j.cossms.2024.101178
Matrangolo PMarchand CNavarro DO’Connor IBosio A(2024)Emerging Technologies for Memory-Centric ComputingDesign and Applications of Emerging Computer Systems10.1007/978-3-031-42478-6_1(3-29)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-42478-6_1
Abbasi RJamshidi V(2023)SBCT-NoC: Ultra Low-Power and Reliable Simultaneous Bi-Directional Current-Mode Transceiver for Network-on-Chip InterconnectsIEEE Transactions on Nanotechnology10.1109/TNANO.2022.320531722(777-784)Online publication date: 2023
https://doi.org/10.1109/TNANO.2022.3205317
Show More Cited By

Index Terms

Ferroelectric Transistor based Non-Volatile Flip-Flop
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware

Recommendations

Nonvolatile memory design based on ferroelectric FETs
DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence ...
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems
ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design

In this work, we propose dual mode ferroelectric transistors (D-FEFETs) that exhibit dynamic tuning of operation between volatile and non-volatile modes with the help of a control signal. We utilize the unique features of D-FEFET to design two variants ...
A magnetic tunnel junction based zero standby leakage current retention flip-flop

Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

August 2016

392 pages

ISBN:9781450341851

DOI:10.1145/2934583

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 August 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Funding Sources

Semiconductor Research Corporation (Global Research Collaboration)

Conference

ISLPED '16

Sponsor:

SIGDA

ISLPED '16: International Symposium on Low Power Electronics and Design

August 8 - 10, 2016

CA, San Francisco Airport, USA

Acceptance Rates

ISLPED '16 Paper Acceptance Rate 60 of 190 submissions, 32%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

34
Total Citations
View Citations
665
Total Downloads

Downloads (Last 12 months)58
Downloads (Last 6 weeks)5

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Leblanc CSong SJariwala D(2024)2D Ferroelectrics and ferroelectrics with 2D: Materials and device prospectsCurrent Opinion in Solid State and Materials Science10.1016/j.cossms.2024.10117832(101178)Online publication date: Sep-2024
https://doi.org/10.1016/j.cossms.2024.101178
Matrangolo PMarchand CNavarro DO’Connor IBosio A(2024)Emerging Technologies for Memory-Centric ComputingDesign and Applications of Emerging Computer Systems10.1007/978-3-031-42478-6_1(3-29)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-42478-6_1
Abbasi RJamshidi V(2023)SBCT-NoC: Ultra Low-Power and Reliable Simultaneous Bi-Directional Current-Mode Transceiver for Network-on-Chip InterconnectsIEEE Transactions on Nanotechnology10.1109/TNANO.2022.320531722(777-784)Online publication date: 2023
https://doi.org/10.1109/TNANO.2022.3205317
Liu RZhang XXie ZWang XLi ZChen XHan YTang M(2023)FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory ComputingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323373642:9(2889-2902)Online publication date: Sep-2023
https://doi.org/10.1109/TCAD.2022.3233736
Kim KKarpov IOlsson RJariwala D(2023)Wurtzite and fluorite ferroelectric materials for electronic memoryNature Nanotechnology10.1038/s41565-023-01361-y18:5(422-441)Online publication date: 27-Apr-2023
https://doi.org/10.1038/s41565-023-01361-y
尹勋岳金黄庆李超蔡嘉杨泽卓成刘明(2022)Computing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFETSCIENTIA SINICA Informationis10.1360/SSI-2021-042052:4(612)Online publication date: 29-Mar-2022
https://doi.org/10.1360/SSI-2021-0420
Thirumala SRaha AGupta SRaghunathan V(2022)Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric TransistorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.312524830:4(365-378)Online publication date: Apr-2022
https://doi.org/10.1109/TVLSI.2021.3125248
Zhang XLiu RSong TYang YHan YChen X(2022)Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.314019441:11(5071-5084)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2021.3140194
Chee HNandha Kumar TAlmurib H(2022)A ReRAM-based Nonvolatile FPGA2022 IEEE 20th Student Conference on Research and Development (SCOReD)10.1109/SCOReD57082.2022.9973999(62-67)Online publication date: 8-Nov-2022
https://doi.org/10.1109/SCOReD57082.2022.9973999
Yan ZHu XShi Y(2022)On the Reliability of Computing-in-Memory Accelerators for Deep Neural NetworksSystem Dependability and Analytics10.1007/978-3-031-02063-6_9(167-190)Online publication date: 26-Jul-2022
https://doi.org/10.1007/978-3-031-02063-6_9
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents