Article

Implications of technology scaling on leakage reduction techniques

Authors:

Y.-F. Tsai,

D. Duarte,

N. Vijaykrishnan,

M. J. IrwinAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 187 - 190

https://doi.org/10.1145/775832.775880

Published: 02 June 2003 Publication History

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Abstract

The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25um, 0.18um, and 0.07um technologies. HSPICE simulation results and estimations with various functional units and memory structures are presented to support a comprehensive analysis.

References

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Narendra, S., et al, "Scaling of stack effect and its application for leakage reduction," ISLPED, pp. 195--200, '01.

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Keshavarzi, et al, "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs," ISLPED, pp 207--212, 2001

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Duarte, D, et al, "Evaluating Run-Time Techniques for Leakage Reduction", ASPDAC, pp. 31--38, 2002

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Ye, Y., Borkar, S., and De, V., "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Sym. on VLSI Circuits, pp. 40--41, 1998

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Halter J., and Najm, F., "A Gate-level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits, IEEE CICC, pp. 475--478, 1997.

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Duarte, D, "Clock Network and Phase-Locked Loop Power Estimation and Experimentation", PhD Thesis, Penn State University, May. 2002

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Cited By

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Subbian VHo F(2012)Power-delay Trade-offs in CMOS Circuits Using Self-bias TransistorsIETE Journal of Research10.4103/0377-2063.9407858:1(24)Online publication date: 2012
https://doi.org/10.4103/0377-2063.94078
Seiculescu CMurali SBenini LMicheli G(2010)Design and Analysis of NoCs for Low-Power 2D and 3D SoCsLow Power Networks-on-Chip10.1007/978-1-4419-6911-8_8(199-222)Online publication date: 27-Aug-2010
https://doi.org/10.1007/978-1-4419-6911-8_8
Figueras JFerr√© APiguet C(2009)Leakage in CMOS Nanometric TechnologiesLow-Power CMOS Circuits10.1201/9781420036503.ch3(1-19)Online publication date: 9-Nov-2009
https://doi.org/10.1201/9781420036503.ch3
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Index Terms

Implications of technology scaling on leakage reduction techniques
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information & Contributors

Information

Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Subbian VHo F(2012)Power-delay Trade-offs in CMOS Circuits Using Self-bias TransistorsIETE Journal of Research10.4103/0377-2063.9407858:1(24)Online publication date: 2012
https://doi.org/10.4103/0377-2063.94078
Seiculescu CMurali SBenini LMicheli G(2010)Design and Analysis of NoCs for Low-Power 2D and 3D SoCsLow Power Networks-on-Chip10.1007/978-1-4419-6911-8_8(199-222)Online publication date: 27-Aug-2010
https://doi.org/10.1007/978-1-4419-6911-8_8
Figueras JFerr√© APiguet C(2009)Leakage in CMOS Nanometric TechnologiesLow-Power CMOS Circuits10.1201/9781420036503.ch3(1-19)Online publication date: 9-Nov-2009
https://doi.org/10.1201/9781420036503.ch3
Wang WHu YHan YLi XZhang Y(2007)Leakage current optimization techniques during test based on don't care bits assignmentJournal of Computer Science and Technology10.1007/s11390-007-9091-x22:5(673-680)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1007/s11390-007-9091-x
Kumar AAnis M(2006)Dual-Vt Design of FPGAs for Subthreshold Leakage ToleranceProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.53(735-740)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.53
Budiu MVenkataramani GChelcea TGoldstein S(2004)Spatial computationACM SIGOPS Operating Systems Review10.1145/1037949.102439638:5(14-26)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037949.1024396
Budiu MVenkataramani GChelcea TGoldstein S(2004)Spatial computationACM SIGARCH Computer Architecture News10.1145/1037947.102439632:5(14-26)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037947.1024396
Budiu MVenkataramani GChelcea TGoldstein S(2004)Spatial computationACM SIGPLAN Notices10.1145/1037187.102439639:11(14-26)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037187.1024396
Budiu MVenkataramani GChelcea TGoldstein SMukherjee SMcKinley K(2004)Spatial computationProceedings of the 11th international conference on Architectural support for programming languages and operating systems10.1145/1024393.1024396(14-26)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1024393.1024396
Gao FHayes J(2004)Exact and heuristic approaches to input vector control for leakage power reductionProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382634(527-532)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382634

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Design & Optimization of FinFET Based Schmitt Trigger Using Leakage Reduction Techniques

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