Browse Theses

In this dissertation we studied optimization problems which, for the most part, involve analysis of switching activity in VLSI circuits. These problems have applications in the areas of low power design and stress testing.

We proposed techniques for minimizing switching activity during test application in scan circuits and combinational circuits tested using BIST. This problem has applications in minimizing power dissipation during test applications. Scan latch ordering along with test vector ordering can give considerable improvement in power dissipation. Note that scan latch ordering techniques have to be applied during synthesis process while test vector ordering can be applied any time before test application. It will also be interesting to see if switching activity and test application time can be reduced at the same time using scan latch ordering. For combinational circuits, greedy heuristic performed better (and faster) than the heuristic with proven performance guarantee. That shows in practice, approximation algorithms with performance guarantee may not be the best heuristic. Experimental results using repetition of vectors showed that if time is not as important criteria as power dissipation, considerable savings can be obtained by repeating some of the test vectors.

We presented a systematic approach towards computing defect oriented stress tests for full integrated scan circuits and purely sequential circuits. These tests can be used during monitored and dynamic burn-in. In case of monitored burn-in, optimal algorithm and fast greedy heuristics are compared in terms of quality of solution obtained and running times. We feel that the greedy heuristic or its variations can compute cyclic stress tests for large circuits where optimal algorithm takes too much time. Computation of defect oriented dynamic stress tests is studied for failures due to (i) electromigration; (ii) hot-electron degradation; and (iii) oxide breakdown. It is observed that a good stress test targeting one defect may not be a good stress test set for another defect. Fast heuristics are developed to compute good defect oriented stress tests. Quality measures that ascertain the effectiveness of the tests to stress these defects as well as their limitations are discussed. It is observed that the switching activity model used accurately models stress due to electromigration. However, it is not as accurate for modeling hot-electron degradation.