Skip header Section
Skip Bibliometrics Section
Logic Design of Digital SystemsFebruary 1978
- Author:
- Donald Leo Dietmeyer
Abstract
No abstract available.
Cited By
- Tarau P and Luderman B Exact combinational logic synthesis and non-standard circuit design Proceedings of the 5th conference on Computing frontiers, (179-188)
- Kagaris D and Haniotakis T (2007). A methodology for transistor-efficient supergate design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:4, (488-492), Online publication date: 1-Apr-2007.
- Kagaris D and Haniotakis T Transistor-Level Optimization of Supergates Proceedings of the 7th International Symposium on Quality Electronic Design, (682-690)
- Sasao T and Butler J (2001). Worst and Best Irredundant Sum-of-Products Expressions, IEEE Transactions on Computers, 50:9, (935-948), Online publication date: 1-Sep-2001.
- Mertzios B and Tsirikolias K (2019). Coordinate logic filters and their applications in image processing and pattern recognition, Circuits, Systems, and Signal Processing, 17:4, (517-538), Online publication date: 1-Jul-1998.
- Biswas N, Srikanth C and Jacob J Cubical CAMP for minimization of Boolean functions Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
- Boubezari S and Kaminska B (1995). A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures, IEEE Transactions on Computers, 44:6, (805-816), Online publication date: 1-Jun-1995.
- Chu Y, Dietmeyer D, Duley J, Hill F, Barbacci M, Rose C, Ordy G, Johnson B and Roberts M (1992). Three Decades of HDLs, IEEE Design & Test, 9:2, (69-81), Online publication date: 1-Apr-1992.
- Dutt S and Hayes J (1991). Subcube Allocation in Hypercube Computers, IEEE Transactions on Computers, 40:3, (341-352), Online publication date: 1-Mar-1991.
- Diaz-Olavarrieta L and Zaky S A new synthesis technique for multilevel combinational circuits Proceedings of the conference on European design automation, (222-227)
- Mensch S and Lipp H Fuzzy specification of finite state machines Proceedings of the conference on European design automation, (622-626)
- Fang K and Wojcik A (2019). Modular Decomposition of Combinatorial Multiple-Values Circuits, IEEE Transactions on Computers, 37:10, (1293-1301), Online publication date: 1-Oct-1988.
- Trevillyan L, Joyner W and Berman L (1986). Global Flow Analysis in Automatic Logic Design, IEEE Transactions on Computers, 35:1, (77-81), Online publication date: 1-Jan-1986.
- Sasao T (1984). Input Variable Assignment and Output Phase Optimization of PLA's, IEEE Transactions on Computers, 33:10, (879-894), Online publication date: 1-Oct-1984.
- Abraham J and Gajski D (1981). Design of Testable Structures Defined by Simple Loops, IEEE Transactions on Computers, 30:11, (875-884), Online publication date: 1-Nov-1981.
- Parker A and Wallace J (1981). Slide, IEEE Transactions on Computers, 30:6, (423-439), Online publication date: 1-Jun-1981.
- Surjaatmadja J (1981). An Algebra for Switching Circuits, IEEE Transactions on Computers, 30:8, (609-613), Online publication date: 1-Aug-1981.
- Agarwal V and Masson G (1980). Generic Fault Characterizations for Table Look-Up Coverage Bounding, IEEE Transactions on Computers, 29:4, (288-299), Online publication date: 1-Apr-1980.
- Darringer J The application of program verification techniques to hardware verification Proceedings of the 16th Design Automation Conference, (375-381)
- vanCleemput W Computer hardware description languages and their applications Proceedings of the 16th Design Automation Conference, (554-560)
- El-ziq Y Logic design automation of MOS combinational networks with fan-in, fan-out constraints Proceedings of the 15th Design Automation Conference, (240-249)
- El-Ziq Y and Su S (1978). Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results, IEEE Transactions on Computers, 27:10, (911-923), Online publication date: 1-Oct-1978.
- Edwards C and Hurst S (1978). A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods, IEEE Transactions on Computers, 27:11, (985-997), Online publication date: 1-Nov-1978.
- Siu-Chong Si (1978). Dynamic Testing of Redundant Logic Networks, IEEE Transactions on Computers, 27:9, (828-832), Online publication date: 1-Sep-1978.
- Ito M and Cameron R (1978). Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays, IEEE Transactions on Computers, 27:9, (833-841), Online publication date: 1-Sep-1978.
- Cerny E and Marin M (1977). An Approach to Unified Methodology of Combinational Switching Circuits, IEEE Transactions on Computers, 26:8, (745-756), Online publication date: 1-Aug-1977.
- Rhyne V, Noe P, Mckinney M and Pooch U (1977). A New Technique for the Fast Minimization of Switching Functions, IEEE Transactions on Computers, 26:8, (757-764), Online publication date: 1-Aug-1977.
- Batni R and Kime C (1976). A Module-Level Testing Approach for Combinational Networks, IEEE Transactions on Computers, 25:6, (594-604), Online publication date: 1-Jun-1976.
- Troxel D (1975). Serial Interfaces for Minicomputers, IEEE Transactions on Computers, 24:10, (1027-1028), Online publication date: 1-Oct-1975.
- Su S (1974). Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973., ACM SIGARCH Computer Architecture News, 3:3, (2-3), Online publication date: 1-Sep-1974.
- Fisher L (1974). Unateness Properties of and-Exclusive-or Logic Circuits, IEEE Transactions on Computers, 23:2, (166-172), Online publication date: 1-Feb-1974.
- Ulug M and Bowen B (1974). A Unified Theory of the Algebraic Topological Methods for the Synthesis of Switching Systems, IEEE Transactions on Computers, 23:3, (255-267), Online publication date: 1-Mar-1974.
- Cerny E and Marin M (1974). A Computer Algorithm for the Synthesis of Memoryless Logic Circuits, IEEE Transactions on Computers, 23:5, (455-465), Online publication date: 1-May-1974.
- Story J, Harrison H and Reinhard E (1972). Optimum State Assignment for Synchronous Sequential Circuits, IEEE Transactions on Computers, 21:12, (1365-1373), Online publication date: 1-Dec-1972.
Please enable JavaScript to view thecomments powered by Disqus.
Recommendations
Proof Systems for a Gödel Modal Logic
TABLEAUX '09: Proceedings of the 18th International Conference on Automated Reasoning with Analytic Tableaux and Related MethodsA basic propositional modal fuzzy logic ${\sf {GK}}_{\Box}$ is defined by combining the Kripke semantics of the modal logic K with the many-valued semantics of Gödel logic G. A sequent of relations calculus is introduced for ${\sf {GK}}_{\Box}$ and a ...
Pure Modal Logic of Names and Tableau Systems
By a pure modal logic of names (PMLN) we mean a quantifier-free formulation of such a logic which includes not only traditional categorical, but also modal categorical sentences with modalities de re and which is an extension of Propositional Logic. For ...