Browse Theses

As process geometries shrink, leakage currents and charge sharing are becoming increasingly critical problems, especially in full-custom circuit designs. Excessive leakage or charge sharing may cause functional failure at some or all operating conditions. Traditional circuit analysis techniques may not properly consider all input constraints for the circuit, so the results may be overly pessimistic. Similar limitations exist for charge sharing.

Successful analysis of high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today's CPU designs make this difficult. A good circuit-level delay model should (1) consider input exclusivity constraints, which represent invalid don't care in put vectors; (2) handle a wide range of circuit structures; and (3) have a robust underlying framework that can be applied independent of the actual device model.

We approach these problems symbolically using Algebraic Decision Diagrams (ADDs), an extension of Binary Decision Diagrams (BDDs). Using ADDs allows us to efficiently perform leakage, charge sharing and timing analysis within a channel-connected region (CCR) as a function of its in puts. All MOS devices in the CCR are modeled as a simple linear resistor or two-port network allowing us to handle any arbitrary circuit structure, including series-parallel network and meshes which have no series-parallel decomposition and can't be merged into a single equivalent device, directly without the need to decompose them into simpler circuits first. The use of ADDs makes the inclusion of exclusivity/input constraints in the analysis easier, thus allowing for a more accurate (and less pessimistic) results. We have applied various heuristics to improve the device model for the circuits without altering the symbolic algorithms. The effectiveness of our approach is demonstrated on full-custom circuits used in actual microprocessor instead of the usual ISCAS or MCNC benchmarks. We show that such an analysis can lead to up to a 90% difference in worst case voltage drop due to leakage and charge sharing. Our worst-case delay estimates are within 10% of SPICE for over 90% of the circuits we simulated. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst-case conditions with other, more costly, simulation techniques.