An evaluation system for distributed-time VHDL simulation

Performance of VHDL simulation is a critical issue in electronic circuit design and is hard to achieve due to the complexity of the language and the different abstraction levels.

This paper presents a system for performance evaluation of distributed-time ...

In this paper we evaluate parallel VHDL simulation based on conservative parallel discrete event simulation (conservative PDES) algorithms. We focus on a conservative simulation algorithm based on critical and external distances. This algorithm exploits ...

In this work, we investigate in a Hardware-in-the-Loop (HiL) approach to solve the problems and opportunities created by the control of large numbers (hundreds to thousands) of MEMS sensors and actuators. Using HiL simulation, one or several devices of ...