article

Free access

FPGA-based configurable systolic architecture for window-based image processing

Authors:

César Torres-Huitzil,

Miguel Arias-EstradaAuthors Info & Claims

EURASIP Journal on Advances in Signal Processing, Volume 2005

Pages 1024 - 1034

https://doi.org/10.1155/ASP.2005.1024

Published: 01 January 2005 Publication History

Abstract

Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of 7×7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7×7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7×7 generic window-based operators on 512×512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.

References

[1]

{1} R. Jain, R. Kasturi, and B. G. Schunck, Machine Vision, McGraw-Hill, New York, NY, USA, international edition, 1995.

Digital Library

[2]

{2} N. Ranganathan, Ed., VLSI & Parallel Computing for Pattern Recognition & Artificial Intelligence, vol. 18 of Series in Machine Perception and Artificial Intelligence, World Scientific Publishing, 1995.

Digital Library

[3]

{3} P. A. Laplante and A. D. Stoyenko, Eds., Real-time Imaging - Theory, Techniques and Applications, IEEE Press, New York, NY, USA, 1996.

Digital Library

[4]

{4} P. M. Athanas and A. L. Abbott, "Real-time image processing on a custom computing platform," Computer, vol. 28, no. 2, pp. 16-24, 1995.

Digital Library

[5]

{5} J. Silc, T. Ungerer, and B. Robic, "A survey of new research directions in microprocessors," Microprocessors and Microsystems , vol. 24, no. 4, pp. 175-190, 2000.

[6]

{6} M. K. Ratha, Computer Vision Algorithms on Reconfigurable Logic Arrays, Ph.D. Dissertation, Michigan State University, 1996.

Digital Library

[7]

{7} B. Bosi, G. Bois, and Y. Savaria, "Reconfigurable pipelined 2- D convolvers for fast digital signal processing," IEEE Trans. VLSI Syst., vol. 7, no. 3, pp. 299-308, 1999.

Digital Library

[8]

{8} R. Managuli, G. York, D. Kim, and Y. Kim, "Mapping of two-dimensional convolution on very long instruction word media processors for real-time performance," Journal of Electronic Imaging, vol. 9, no. 3, pp. 327-335, 2000.

[9]

{9} D.H. Ballard and C.M. Brown, Computer Vision, Prentice-Hall, Englewood Cliffs, NJ, USA, 1982.

Digital Library

[10]

{10} D. Li, L. Jiang, and H. Kunieda, "Design optimization of vlsi array processor architecture for window image processing," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E82-A, no. 8, pp. 1475-1484, 1999.

[11]

{11} A. Bouridane, D. Crookes, P. Donachy, K. Alotaibi, and K. Benkrid, "A high level FPGA-based abstract machine for image processing," Journal of Systems Architecture, vol. 45, no. 10, pp. 809-824, 1999.

Digital Library

[12]

{12} V. Moshnyaga, N. Watanabe, and K. Tamaru, "A memory efficient array architecture for real-time motion estimation," IEICE Transactions, vol. J81-D-I, no. 2, pp. 77-85, 1998.

[13]

{13} A. DeHon, "The density advantage of configurable computing," Computer, vol. 33, no. 4, pp. 41-49, 2000.

Digital Library

[14]

{14} P. Marchal, "Field-programmable gate arrays," Communications of the ACM, vol. 42, no. 4, pp. 57-59, 1999.

Digital Library

[15]

{15} M. Arias-Estrada and C. Torres-Huitzil, "Real-time field programmable gate array architecture for computer vision," Journal of Electronic Imaging, vol. 10, no. 1, pp. 289-296, 2001.

[16]

{16} B. Draper, W. Najjar, W. Böhm, et al., "Compiling and optimizing image processing algorithms for FPGA's," in International Workshop on Computer Architecture for Machine Performance (CAMP '00), pp. 240-246, Padova, Italy, September 2000.

Digital Library

[17]

{17} F. Lohier, Méthodologies de programmation et évaluation des processeurs de traitement de signal paralleles por le traitement d'images en temps réel, Ph.D. Dissertation, L'Universite Pierre Et Marie Curie (Paris 6), 2000.

[18]

{18} H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. Chaves Filho, "Morphosys: an integrated reconfigurable system for data-parallel and computation-intensive applications," IEEE Trans. Comput., vol. 49, no. 5, pp. 465-481, 2000.

Digital Library

Cited By

Arumalla AMakkena M(2022)Efficient Architecture for Block Parallel Convolution using Two-Dimensional Polyphase DecompositionCircuits, Systems, and Signal Processing10.1007/s00034-021-01811-941:2(1166-1186)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s00034-021-01811-9
Torres-Huitzil C(2016)FPGA-based fast computation of gray-level morphological granulometriesJournal of Real-Time Image Processing10.1007/s11554-013-0355-011:3(547-557)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1007/s11554-013-0355-0
Huang MSerres OEl-Ghazawi TNewby G(2010)Parameterized hardware design on reconfigurable computersInternational Journal of Reconfigurable Computing10.1155/2010/4545062010(5-5)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/454506
Show More Cited By

Index Terms

FPGA-based configurable systolic architecture for window-based image processing

Recommendations

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA
Abstract
Evolvable hardware is a system that modifies its architecture and behavior to adapt with changes of the environment. It is formed by reconfigurable processing elements driven by an evolutionary algorithm. In this paper, we study a reconfigurable ...
Design and evaluation of a hardware/software FPGA-based system for fast image processing

We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host ...
FPGA-based hardware accelerator for high-performance data-stream processing

An approach to solving high-performance data-stream processing is proposed based on hardware solutions that use a field-programmable gate array. The described HDG hardware solution was successfully applied to video data streams. The computation capacity ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image EURASIP Journal on Advances in Signal Processing

EURASIP Journal on Advances in Signal Processing Volume 2005, Issue

1 January 2005

3208 pages

ISSN:1110-8657

Issue’s Table of Contents

Publisher

Hindawi Limited

London, United Kingdom

Publication History

Published: 01 January 2005

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
373
Total Downloads

Downloads (Last 12 months)12
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Arumalla AMakkena M(2022)Efficient Architecture for Block Parallel Convolution using Two-Dimensional Polyphase DecompositionCircuits, Systems, and Signal Processing10.1007/s00034-021-01811-941:2(1166-1186)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s00034-021-01811-9
Torres-Huitzil C(2016)FPGA-based fast computation of gray-level morphological granulometriesJournal of Real-Time Image Processing10.1007/s11554-013-0355-011:3(547-557)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1007/s11554-013-0355-0
Huang MSerres OEl-Ghazawi TNewby G(2010)Parameterized hardware design on reconfigurable computersInternational Journal of Reconfigurable Computing10.1155/2010/4545062010(5-5)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/454506
Fabiani E(2009)Experiencing a problem-based learning approach for teaching reconfigurable architecture designInternational Journal of Reconfigurable Computing10.1155/2009/9234152009(1-1)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/923415
Dong YDou YLiu M(2008)A design space exploration algorithm in compiling window operation onto reconfigurable hardwareInternational Journal of Computers and Applications10.1080/1206212X.2008.1144188130:1(36-43)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1080/1206212X.2008.11441881

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents