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The IBM System/370 vector architecture

Author:

W. BuchholzAuthors Info & Claims

IBM Systems Journal, Volume 25, Issue 1

Pages 51 - 62

https://doi.org/10.1147/sj.251.0051

Published: 01 January 1986 Publication History

Abstract

Discussed is the instruction-set architecture of the IBM System/370 vector facility, a compatible extension of the System/370 architecture. Both the base system, which is a general-purpose System/370 processor, and the optional vector facility employ a register type of organization. Data formats are the same, arithmetic operations produce exactly the same results, arithmetic exceptions are handled in the same way, and instructions are precisely interruptible for page faults and other causes in the same manner as those of the base system. This approach permits substantially increased performance on vectorizable programs with only a modest increase in hardware and software, while retaining the ability to run existing nonvector programs unchanged.

References

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IBM Systems Journal Volume 25, Issue 1

March 1986

127 pages

ISSN:0018-8670

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IBM Corp.

United States

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Published: 01 January 1986

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Tanasic IGelado IJorda MAyguade ENavarro NHunter HMoreno JEmer JSanchez D(2017)Efficient exception handling support for GPUsProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123950(109-122)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123950
Lee YAvizienis RBishara AXia RLockhart DBatten CAsanović K(2013)Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel AcceleratorsACM Transactions on Computer Systems10.1145/249146431:3(1-38)Online publication date: 1-Aug-2013
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Hampton MAsanović KEgan GMuraoka Y(2006)Implementing virtual memory in a vector processor with software restart markersProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183422(135-144)Online publication date: 28-Jun-2006
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Vassiliadis SWong SGaydadjiev GBertels KKuzmanov GPanainte E(2004)The MOLEN Polymorphic ProcessorIEEE Transactions on Computers10.1109/TC.2004.10453:11(1363-1375)Online publication date: 1-Nov-2004
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Vassiliadis SCotofana SStathis P(1999)Vector ISA Extension for Sparse Matrix-Vector MultiplicationProceedings of the 5th International Euro-Par Conference on Parallel Processing10.5555/646664.700449(708-715)Online publication date: 31-Aug-1999
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Reuter RScharffenberger USchüle J(1991)Multiplication of a symmetric banded matrix by a vector on a vector multiprocessor computerIBM Journal of Research and Development10.1147/rd.355.069735:5-6(697-706)Online publication date: 15-Sep-1991
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Arnold RHalpern PHogsett GStraka BArasmith CMcElroy J(1991)A numerically intensive computing environmentIBM Journal of Research and Development10.1147/rd.351.014035:1-2(140-155)Online publication date: 1-Mar-1991
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Chiueh T(1991)Multi-threaded vectorizationACM SIGARCH Computer Architecture News10.1145/115953.11598719:3(352-361)Online publication date: 1-Apr-1991
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Chiueh TVranesic Z(1991)Multi-threaded vectorizationProceedings of the 18th annual international symposium on Computer architecture10.1145/115952.115987(352-361)Online publication date: 1-Apr-1991
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Borden THennessy JRymarczyk J(1989)The facilities and evolution of MVS/ESAIBM Systems Journal10.1147/sj.281.012428:1(124-150)Online publication date: 1-Mar-1989
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Dynamic Profile of Instruction Sequences for the IBM System/370

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