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Modeling of integrated circuit defect sensitivities

Author:

C. H. StapperAuthors Info & Claims

IBM Journal of Research and Development, Volume 27, Issue 6

Pages 549 - 557

https://doi.org/10.1147/rd.276.0549

Published: 01 November 1983 Publication History

Abstract

Until now only cursory descriptions of mathematical models for defect sensitivities of integrated circuit chips have been given in the yield literature. This paper treats the fundamentals of the defect models that have been used successfully at IBM for a period of more than fifteen years. The effects of very small defects are discussed first. The case of photolithographic defects, which are of the same dimensions as the integrated circuit device and interconnection patterns, is dealt with in the remainder of the paper. The relationships between these models and test sites are described. Data from measurements of defect sizes are discussed.

References

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cover image IBM Journal of Research and Development

IBM Journal of Research and Development Volume 27, Issue 6

November 1983

77 pages

ISSN:0018-8646

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IBM Corp.

United States

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Published: 01 November 1983

Received: 20 May 1983

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Gupte AVyas SJones P(2015)A Fault-Aware Toolchain Approach for FPGA Fault ToleranceACM Transactions on Design Automation of Electronic Systems10.1145/269983820:2(1-22)Online publication date: 2-Mar-2015
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Chen XZhu JWawrzynek JCompton K(2011)Regular fabric for regular FPGA (abstract only)Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950484(284-284)Online publication date: 27-Feb-2011
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Ghaida RZarkesh-Ha P(2009)A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow InterconnectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-008-5079-x25:1(67-77)Online publication date: 1-Feb-2009
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Sreedhar ASanyal AKundu SSciuto D(2008)On modeling and testing of lithography related open faults in nano-CMOS circuitsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403525(616-621)Online publication date: 10-Mar-2008
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Zarkesh-Ha PDoniger KKennings AMandoiu I(2007)Stochastic interconnect layout sensitivity modelProceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231959(9-14)Online publication date: 17-Mar-2007
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Nelson JZanon TDesineni RBrown JPatil NMaly WBlanton RGielen G(2006)Extraction of defect density and size distributions from wafer sort test resultsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131737(913-918)Online publication date: 6-Mar-2006
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