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The design of the fixed point unit for the z990 microprocessor

Published: 26 April 2004 Publication History

Abstract

The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.

References

[1]
Glenn Hinton et. al, "A 0.18-um CMOS IA-32 Processor With a 4-GHz Integer Execution Unit," IEEE Journal of Solid State Circuits, Vol. 36, No. 11, Nov. 2001.
[2]
T. J. Slegel, E. Pfeffer, J. A. Magee, "The IBM eServer z990 microprocessor," IBM Journal of Research and Development, vol. 48, no. 3/4 (accepted for publication in the May/July 2004 issue)
[3]
T. McPherson and et al. "760 MHz G6 S/390 Microprocessor Exploiting Multiple Vt and Copper Interconnects", Solid-State Circuits Conference, Feb. 2000.
[4]
G. Northrop and et. Al "600 MHz G5 S/390 Microprocessor", 1999 International Solid-State Circuits Conference, Feb. 1999, pp. 88--89.
[5]
Timothy . Slegel and et al. "IBM S/390 G5 Microprocessor", 1998 Hot Chips Symposium, Stanford. Aug., 1998.
[6]
F. Busaba, et. al, "The IBM z900 Decimal Arithmetic Unit, "35th Asilomar Conference on Signals, Systems and Computers, Nov. 2001.
[7]
F. Busaba, and et. al, "Designer-Level Logic Verification Using RuleBase, "4th International Workshop of Testing Embedded Core-based System-Chips, Montreal, May 2000.
[8]
A Chandra, V. Avenger, D. Gist and Y. Wolfs Hal, "AVPGEN-A Test Generator for Architecture Verification," IEEE Trans. Very Large Scale Integration (VLSI) sys. Vol. 3, No. 2, pp. 188--200, June 1985.

Cited By

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  • (2021)Investigations on Decimal Multipliers through Novel Partial Product GeneratorsJournal of The Institution of Engineers (India): Series B10.1007/s40031-021-00657-8103:2(507-516)Online publication date: 13-Sep-2021
  • (2021)Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 EncodingsRecent Trends in Electronics and Communication10.1007/978-981-16-2761-3_32(345-353)Online publication date: 14-Dec-2021
  • (2021)The VLSI Realization of Sign-Magnitude Decimal Multiplication EfficiencyModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-030-68291-0_39(489-505)Online publication date: 27-Apr-2021
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    cover image ACM Conferences
    GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI
    April 2004
    479 pages
    ISBN:1581138539
    DOI:10.1145/988952
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    Publication History

    Published: 26 April 2004

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    Author Tags

    1. microprocessor
    2. superscalar FXU

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    GLSVLSI04: Great Lakes Symposium on VLSI 2004
    April 26 - 28, 2004
    MA, Boston, USA

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    Cited By

    View all
    • (2021)Investigations on Decimal Multipliers through Novel Partial Product GeneratorsJournal of The Institution of Engineers (India): Series B10.1007/s40031-021-00657-8103:2(507-516)Online publication date: 13-Sep-2021
    • (2021)Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 EncodingsRecent Trends in Electronics and Communication10.1007/978-981-16-2761-3_32(345-353)Online publication date: 14-Dec-2021
    • (2021)The VLSI Realization of Sign-Magnitude Decimal Multiplication EfficiencyModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-030-68291-0_39(489-505)Online publication date: 27-Apr-2021
    • (2019)Decimal Hardware MultiplierAdvanced Methodologies and Technologies in Artificial Intelligence, Computer Simulation, and Human-Computer Interaction10.4018/978-1-5225-7368-5.ch054(722-736)Online publication date: 2019
    • (2018)Decimal Hardware MultiplierEncyclopedia of Information Science and Technology, Fourth Edition10.4018/978-1-5225-2255-3.ch400(4607-4618)Online publication date: 2018
    • (2017)High Performance Parallel Decimal Multipliers Using Hybrid BCD CodesIEEE Transactions on Computers10.1109/TC.2017.270626266:12(1994-2004)Online publication date: 1-Dec-2017
    • (2015)Implementation of high speed radix-10 parallel multiplier using Verilog2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208074(1-5)Online publication date: Jun-2015
    • (2015)Implementation of high speed radix-10 parallel multiplier using Verilog2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208073(1-5)Online publication date: Jun-2015
    • (2015)Area-efficient and power-efficient binary to BCD convertersProceedings of the 2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT)10.1109/ICCCNT.2015.7395189(1-7)Online publication date: 13-Jul-2015
    • (2014)Hardware Design for Decimal MultiplicationEncyclopedia of Information Science and Technology, Third Edition10.4018/978-1-4666-5888-2.ch538(5455-5464)Online publication date: 31-Jul-2014
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