Article

Transaction level modeling: an overview

Authors:

Daniel GajskiAuthors Info & Claims

CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 19 - 24

https://doi.org/10.1145/944645.944651

Published: 01 October 2003 Publication History

Abstract

Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated. This paper introduces a TLM taxonomy and compares the benefits of TLMs' use.

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Cited By

Cheremisinov DCheremisinova L(2023)Simulation of discrete control systems with parallelism of behaviorInformatics10.37661/1816-0301-2023-20-4-24-3720:4(24-37)Online publication date: 29-Dec-2023
https://doi.org/10.37661/1816-0301-2023-20-4-24-37
(2023)ReferencesComputers as Components10.1016/B978-0-323-85128-2.16001-3(505-518)Online publication date: 2023
https://doi.org/10.1016/B978-0-323-85128-2.16001-3
Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
https://dl.acm.org/doi/10.1145/3510578
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Index Terms

Transaction level modeling: an overview
1. Computer systems organization

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Published In

cover image ACM Conferences

CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2003

242 pages

ISBN:1581137427

DOI:10.1145/944645

General Chairs:
Rajesh Gupta
University of California, San Diego
,
Yukihiro Nakamura
Kyoto University, Japan
,
Program Chairs:
Alex Orailoglu
University of California, San Diego
,
Pai H. Chou
University of California, Irvine

Copyright © 2003 ACM.

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Published: 01 October 2003

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CODES+ISSS03: First IEEE/ACM/IFIP International CODES + ISSS 2003 Merged Conference

October 1 - 3, 2003

CA, Newport Beach, USA

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Cited By

Cheremisinov DCheremisinova L(2023)Simulation of discrete control systems with parallelism of behaviorInformatics10.37661/1816-0301-2023-20-4-24-3720:4(24-37)Online publication date: 29-Dec-2023
https://doi.org/10.37661/1816-0301-2023-20-4-24-37
(2023)ReferencesComputers as Components10.1016/B978-0-323-85128-2.16001-3(505-518)Online publication date: 2023
https://doi.org/10.1016/B978-0-323-85128-2.16001-3
Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
https://dl.acm.org/doi/10.1145/3510578
Herget MSaadatmand FBor MAlonso IStefanov TAkesson BPimentel A(2022)Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions2022 25th Euromicro Conference on Digital System Design (DSD)10.1109/DSD57027.2022.00090(632-640)Online publication date: Aug-2022
https://doi.org/10.1109/DSD57027.2022.00090
Pimentel A(2022)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-15-6401-7_23-1(1-31)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_23-1
Marwedel PMarwedel P(2021)Specifications and ModelingEmbedded System Design10.1007/978-3-030-60910-8_2(29-126)Online publication date: 26-Jan-2021
https://doi.org/10.1007/978-3-030-60910-8_2
Harris IHarris C(2020)Generation of Verification Artifacts from Natural Language DescriptionsNatural Language Processing for Electronic Design Automation10.1007/978-3-030-52273-5_3(37-70)Online publication date: 1-Sep-2020
https://doi.org/10.1007/978-3-030-52273-5_3
Nours SPostula A(2018)A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources ConflictsJournal of Signal Processing Systems10.5555/3288382.328840590:12(1667-1685)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.5555/3288382.3288405
Kakani RDarji A(2018)Transactional Test Environment for Faster and Early Verification of Digital Designs2018 International Conference on Computing, Engineering, and Design (ICCED)10.1109/ICCED.2018.00037(148-152)Online publication date: Sep-2018
https://doi.org/10.1109/ICCED.2018.00037
Gregorek DGarcia-Ortiz A(2018)The Agamid design-space exploration frameworkDesign Automation for Embedded Systems10.1007/s10617-018-9214-322:4(293-314)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1007/s10617-018-9214-3
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