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Limits on multiple instruction issue

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M. A. HorowitzAuthors Info & Claims

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

Pages 290 - 302

https://doi.org/10.1145/70082.68209

Published: 01 April 1989 Publication History

Abstract

This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.

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Published In

cover image ACM Conferences

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

April 1989

303 pages

ISBN:0897913000

DOI:10.1145/70082

Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

ACM SIGARCH Computer Architecture News Volume 17, Issue 2
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems
April 1989
291 pages
ISSN:0163-5964
DOI:10.1145/68182
Editor:
Joel Emer
Issue’s Table of Contents

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 April 1989

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ASPLOS89: Int'l Conference on Architecture Support for Programming Lang & Operating Systems

April 3 - 6, 1989

Massachusetts, Boston, USA

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Bera RRanganathan ARakshit JMahto SNori AGaur JOlgun AKanellopoulos KSadrosadati MSubramoney SMutlu O(2024)Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00017(88-102)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00017
Hu XBurgstaller BScholz B(2023)EVMTracer: Dynamic Analysis of the Parallelization and Redundancy Potential in the Ethereum Virtual MachineIEEE Access10.1109/ACCESS.2023.326727711(47159-47178)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3267277
Chien ELevi ZWeber O(2016)Bounded distortion parametrization in the space of metricsACM Transactions on Graphics10.1145/2980179.298242635:6(1-16)Online publication date: 5-Dec-2016
https://dl.acm.org/doi/10.1145/2980179.2982426
Hedman PRitschel TDrettakis GBrostow G(2016)Scalable inside-out image-based renderingACM Transactions on Graphics10.1145/2980179.298242035:6(1-11)Online publication date: 5-Dec-2016
https://dl.acm.org/doi/10.1145/2980179.2982420
Malomo LPietroni NBickel BCignoni P(2016)FlexMoldsACM Transactions on Graphics10.1145/2980179.298239735:6(1-12)Online publication date: 5-Dec-2016
https://dl.acm.org/doi/10.1145/2980179.2982397
Xu ZNielsen JYu JJensen HRamamoorthi R(2016)Minimal BRDF sampling for two-shot near-field reflectance acquisitionACM Transactions on Graphics10.1145/2980179.298239635:6(1-12)Online publication date: 5-Dec-2016
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Aiken ABanerjee UKejariwal ANicolau AAiken ABanerjee UKejariwal ANicolau A(2016)IntroductionInstruction Level Parallelism10.1007/978-1-4899-7797-7_1(1-7)Online publication date: 30-Nov-2016
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Malazgirt GYurdakul ANiar S(2015)Customizing VLIW processors from dynamically profiled execution tracesMicroprocessors & Microsystems10.1016/j.micpro.2015.09.00539:8(656-673)Online publication date: 1-Nov-2015
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August D(2010)Branch PredicationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch5(109-133)Online publication date: 14-Jan-2010
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