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Analog circuit sizing based on formal methods using affine arithmetic

Published: 10 November 2002 Publication History

Abstract

We present a novel approach to optimization-based variation-tolerant analog circuit sizing. Using formal methods based on affine arithmetic, we calculate guaranteed bounds on the worst-case behavior and deterministically find the global optimum of the sizing problem by means of branch-and-bound optimization. To solve the nonlinear circuit equations with parameter variations, we define a novel affine-arithmetic Newton operator that gives a significant improvement in computational efficiency over an implementation using interval arithmetic. The calculation of guaranteed worst-case bounds and the global optimization are demonstrated by a prototype implementation.

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cover image ACM Conferences
ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
November 2002
793 pages
ISBN:0780376072
DOI:10.1145/774572
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 10 November 2002

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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  • (2023)ReferencesInterval Methods for Uncertain Power System Analysis10.1002/9781119855071.ref(112-118)Online publication date: 14-Jul-2023
  • (2015)Towards enhancing analog circuits sizing using SMT-based techniquesProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744919(1-6)Online publication date: 7-Jun-2015
  • (2013)Verification of mixed-signal systems with affine arithmetic assertionsVLSI Design10.1155/2013/2390642013(5-5)Online publication date: 1-Jan-2013
  • (2008)Probabilistic Interval-Valued ComputationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200614227:12(2317-2330)Online publication date: 1-Dec-2008
  • (2006)Probabilistic interval-valued computationProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146955(167-172)Online publication date: 24-Jul-2006
  • (2006)Statistical timing based on incomplete probabilistic descriptions of parameter uncertaintyProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146954(161-166)Online publication date: 24-Jul-2006
  • (2006)A practical approach for monitoring analog circuitsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127984(330-335)Online publication date: 30-Apr-2006
  • (2004)Refinement of Mixed-Signal Systems with Affine ArithmeticProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969096Online publication date: 16-Feb-2004
  • (2004)Towards formal verification of analog designsProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382573(210-217)Online publication date: 7-Nov-2004
  • (2004)Refinement of mixed-signals systems with affine arithmeticProceedings Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2004.1268875(372-377)Online publication date: 2004
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