Article

Free access

Efficient floorplan area optimization

Authors:

D. F. Wong,

P. S. SakhamuriAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 586 - 589

https://doi.org/10.1145/74382.74481

Published: 01 June 1989 Publication History

PDF eReader

Abstract

The floorplan area optimization problem is to determine the shape and dimensions of all the modules when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. Existing methods only apply to slicing floorplans. We present in this paper an algorithm for general hierarchical floorplans. Our algorithm combines the curve-adding technique used in the case of slicing floorplans and a new technique that computes shape curves by iterative modification of the shape and dimensions of individual modules. We also present an optimal points selection algorithm using the technique of dynamic programming to further enhance the process of shape curves construction.

References

[1]

Aho, A. V., J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley Publishing Company, (1974).

Digital Library

Google Scholar

[2]

Dai, Wei-Ming and E. S. Kuh, "Simultaneous Floor Planning and Gtobal Routing for Hierarchical Building-Block Layout," {EEE Trans. on CAD, Vol. CAD.6. NO.5. (1987), 828-837.

Google Scholar

[3]

Lauther, U., "A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation," Journal of Digital Systeme, Vol. IV, Issue 1, (1980), 21-34.

Google Scholar

[4]

Otten, R. H. J. M., "Automatic Floorplan Design," Proc. 19th ACM/IEEE Design Automation Conf., (1982), 261-267.

Digital Library

Google Scholar

[5]

Otten, R. H. M., "Efficient Floorplan Optimization," Proc. ICCD 83, (1983), 499-502.

Google Scholar

[6]

Preas, B. and W. M. VanCleemput, "Placement Algorithms for Arbitrary Shaped B.locks," Proc. I6~h ACM{IEEE Design Automation Conf., (1979), 474-480.

Digital Library

Google Scholar

[7]

Stockmeyer, L., "Optimal Orientations of Ceils in Slicing Floorplan Designs," Information and Control, Vol.59, (1983),91-101.

Digital Library

Google Scholar

[8]

Wong, D. F. and C. L, Liu, "A New Algorithm for Floorplan Design," Proc. 23rd ACM/IEEE Design Automalion Conf., (I986), 101-107.

Digital Library

Google Scholar

[9]

Wong, D. F. and C. L. Liu, "Floorplan Design for Rectangular and L-Shaped Modules", Proc. IEEE Intl. Conf. on CompuIer-Aided-Design, (1987), 520-523,

Google Scholar

Cited By

View all

R SKarjigi VNaik HKumar VMarathe K(2022)Development of Automation Tool for Optimising Floorplan of a Given VLSI Design2022 IEEE 19th India Council International Conference (INDICON)10.1109/INDICON56171.2022.10039739(1-6)Online publication date: 24-Nov-2022
https://doi.org/10.1109/INDICON56171.2022.10039739
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Chip PlanningVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_3(53-93)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_3
Chu ZXia YWang LWang J(2014)Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engineMicroelectronics Journal10.1016/j.mejo.2014.01.00645:4(382-393)Online publication date: Apr-2014
https://doi.org/10.1016/j.mejo.2014.01.006
Show More Cited By

Index Terms

Efficient floorplan area optimization
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
    2. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design

Recommendations

Area optimization of floorplan designs
Area reduction by deadspace utilization on interconnect optimized floorplan

Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the ...
Graph-Based Techniques for Hierarchical Floorplan Area Optimization

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC89

Sponsor:

IEEE-CS\TCDA
SIGDA

DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

Acceptance Rates

DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

39
Total Citations
View Citations
674
Total Downloads

Downloads (Last 12 months)51
Downloads (Last 6 weeks)5

Reflects downloads up to 18 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

R SKarjigi VNaik HKumar VMarathe K(2022)Development of Automation Tool for Optimising Floorplan of a Given VLSI Design2022 IEEE 19th India Council International Conference (INDICON)10.1109/INDICON56171.2022.10039739(1-6)Online publication date: 24-Nov-2022
https://doi.org/10.1109/INDICON56171.2022.10039739
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Chip PlanningVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_3(53-93)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_3
Chu ZXia YWang LWang J(2014)Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engineMicroelectronics Journal10.1016/j.mejo.2014.01.00645:4(382-393)Online publication date: Apr-2014
https://doi.org/10.1016/j.mejo.2014.01.006
Hui Dai Jinian Bian Qiang Zhou Zhipeng Liu (2007)A Novel Incremental Floorplan Algorithm for Duplication in Integration of High-level Synthesis and Floorplan2007 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2007.4348253(1163-1167)Online publication date: Jul-2007
https://doi.org/10.1109/ICCCAS.2007.4348253
Bazargan KKim SSarrafzadeh M(2006)NostradamusIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.75292318:4(389-397)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.752923
Pan PLiu C(2006)Area minimization for floorplansIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.36311914:1(123-132)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.363119
Yeap GSarrafzadeh M(2006)A unified approach to floorplan sizing and enumerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25114912:12(1858-1867)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.251149
Wang TWong D(2006)Optimal floorplan area optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.14977011:8(992-1002)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.149770
Sutanthavibul SShragowitz ERosen J(2006)An analytical approach to floorplan design and optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.13750510:6(761-769)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.137505
Khoo WSaratchandran PSundararajan N(2003)Constrained two dimensional bin packing using a genetic algorithmRecent advances in intelligent paradigms and applications10.5555/885831.885842(187-210)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.5555/885831.885842
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Area optimization of floorplan designs

Area reduction by deadspace utilization on interconnect optimized floorplan

Graph-Based Techniques for Hierarchical Floorplan Area Optimization