Article

Interconnect enhancements for a high-speed PLD architecture

Authors:

Michael Hutton,

Peter Kazarian,

Bruce Pedersen,

Jay Schleicher,

Sergey ShumarayevAuthors Info & Claims

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Pages 3 - 10

https://doi.org/10.1145/503048.503050

Published: 24 February 2002 Publication History

Abstract

As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.

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Cited By

Nikolić SZgheib GIenne P(2022)Detailed Placement for Dedicated LUT-Level FPGA InterconnectACM Transactions on Reconfigurable Technology and Systems10.1145/350180215:4(1-33)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3501802
Nikolić SZgheib GIenne PNeuendorffer SShannon L(2020)Straight to the PointProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375315(150-160)Online publication date: 23-Feb-2020
https://dl.acm.org/doi/10.1145/3373087.3375315
Nikolic SZgheib GIenne P(2020)Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00035(153-161)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00035
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Published In

cover image ACM Conferences

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

February 2002

257 pages

ISBN:1581134525

DOI:10.1145/503048

General Chair:
Martine Schlag,
Program Chair:
Steve Trimberger

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

Publication History

Published: 24 February 2002

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FPGA02

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SIGDA

FPGA02: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 24 - 26, 2002

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Nikolić SZgheib GIenne P(2022)Detailed Placement for Dedicated LUT-Level FPGA InterconnectACM Transactions on Reconfigurable Technology and Systems10.1145/350180215:4(1-33)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3501802
Nikolić SZgheib GIenne PNeuendorffer SShannon L(2020)Straight to the PointProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375315(150-160)Online publication date: 23-Feb-2020
https://dl.acm.org/doi/10.1145/3373087.3375315
Nikolic SZgheib GIenne P(2020)Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00035(153-161)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00035
Gaillardon PO’Connor IClermidy FGaillardon PO’Connor IClermidy F(2012)Background and MotivationDisruptive Logic Architectures and Technologies10.1007/978-1-4614-3058-2_2(17-43)Online publication date: 24-Apr-2012
https://doi.org/10.1007/978-1-4614-3058-2_2
Kuon IRose J(2011)Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203131819:1(71-84)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031318
Teehan PLemieux GGreenstreet MChow PCheung P(2009)Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508136(43-52)Online publication date: 24-Feb-2009
https://dl.acm.org/doi/10.1145/1508128.1508136
Anderson JNajm F(2009)Low-power programmable FPGA routing circuitryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201744317:8(1048-1060)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017443
Kuon IRose JHutton MChow P(2008)Area and delay trade-offs in the circuit and architecture design of FPGAsProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344695(149-158)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344695
Lin MEl Gamal ADeHon AHutton M(2007)A routing fabric for monolithically stacked 3D-FPGAProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216921(3-12)Online publication date: 18-Feb-2007
https://dl.acm.org/doi/10.1145/1216919.1216921
Lin MEl Gamal ALu YWong S(2007)Performance Benefits of Monolithically Stacked 3-D FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88792026:2(216-229)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.887920
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