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A cache coherence approach for large multiprocessor systems

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J. K. ArchibaldAuthors Info & Claims

ICS '88: Proceedings of the 2nd international conference on Supercomputing

Pages 337 - 345

https://doi.org/10.1145/55364.55397

Published: 01 June 1988 Publication History

Abstract

This paper explores the architecture of high-performance large scale multiprocessors using private caches for each processor. The caches reduce the average memory access time, but they also result in the well known cache coherence problem. Multiple copies of each memory location are allowed to exist but they must be kept consistent with each other. In this paper, we present a solution to the cache coherence problem specifically for shared bus multiprocessors that adapts dynamically to the reference pattern. Simulation results are presented that demonstrate the high level of performance relative to other protocols particularly during intervals with high levels of sharing.

The paper then presents a coherence solution for large multiprocessor systems organized around a hierarchy of buses. One of the first solutions of this kind, the hierarchical protocol is an extension of the adaptive shared bus approach described in this paper.

References

[1]

J. Archibald. The Cache Coherence Problem in Shared- Memory Multiprocessors. PhD Thesis~ University of Washington, March 1987.

Digital Library

[2]

J. Archibald. High Performance Cache Coherence Protocols For Shared-Bus Multiprocessors. Technical Report Tit 86-06-02, Department of Computer Science, University of Washington, Seattle, WA 98195, June 1986.

[3]

J. Archibald and J.-L. Boer. Cache coherence protocols: evaluation using a multiprocessor simulation model. A CM Transactions or, Computer Systems, 4(4):273-298, November 1986.

Digital Library

[4]

J.-L. Boer and W.-H. Wang. Architectural choices for multi-level cache hierarchies. In Proc. of 16th Int. Conf. on Parallel Processing, pages 258-261, IEEE, 1987.

[5]

J.-L. Baer and W.-H. Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. Technical Report TR- 87-11-08, Dept. of Computer Science, University of Washiugton, Seattle, WA 98195, November 1987.

[6]

M. Dubois and F. B riggs. Effects of cache coherency in multiprocessors. IEEE Transactions on Computers, C- 31(11):1083-1099, November 1982.

Digital Library

[7]

S. Eggers and It. Katz. Characterization of sharing in parallel programs and its applicability to coherency protocol evaluation. In Proc. of 15th Int. Syrup. on Computer Architecture, IEEE, 1988.

Digital Library

[8]

S. J. Frank. Tightly coupled multiprocessor systems speed memory access times. Electronics, 57(1):164-169, January 1984.

[9]

J. R. Goodman. Using cache memory to reduce processormemory traffic, in Proc. of l Oth Int. Syrup. on Computer Architecture, pages 124-131, IEEE, 1983.

Digital Library

[10]

R. Katz, S. Eggers, D. A. Wood, C. Perkins, and R. G. Sheldon. Implementing a cache consistency protocol. In Proc. of 12th Int. Syrup. on Computer Architecture, pages 276-283, IEEE, 1985.

Digital Library

[11]

E. McCreight. The Dragon Computer System: An Early Overview. Technical Report, Xerox Corp., September 1984.

[12]

M. Papamarcos and J. Patel. A low overhead coherence solution for multiprocessors with private cache memories. In Proc. of 11th Int. Syrup. on Computer Architecture, pages 348-354, IEEE, 1984.

Digital Library

[13]

L. Rudolph and Z. Segall. Dynamic decentralized cache schemes for MIMD parallel processors, in Proc. o.f 11th Int. Syrup. on Computer Architecture, pages 340-347, IEEE, 1984.

Digital Library

[14]

M. C. Shebanow and Y. N. Patt. The adaptive cache coherence protocol-a predictive based solution to the cache coherence problem. Forthcoming paper.

[15]

A. W. Wilson Jr. Hierarchical cache/bus architecture for shared memory multiprocessors. In Proc. o} 14th Int. Syrup. on Computer Architecture, pages 244-252, IEEE, 1987.

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Cited By

Chang JHerrero ECanal RSohi G(2011)Cooperative Caching for Chip MultiprocessorsCooperative Networking10.1002/9781119973584.ch13(217-275)Online publication date: 13-Jul-2011
https://doi.org/10.1002/9781119973584.ch13
Chapman MHeiser G(2009)vNUMAProceedings of the 2009 conference on USENIX Annual technical conference10.5555/1855807.1855809(2-2)Online publication date: 14-Jun-2009
https://dl.acm.org/doi/10.5555/1855807.1855809
Chtioui HAtitallah RNiar SDekeyser JAbid M(2009)A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.220(3-10)Online publication date: 27-Aug-2009
https://dl.acm.org/doi/10.1109/DSD.2009.220
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cover image ACM Conferences

ICS '88: Proceedings of the 2nd international conference on Supercomputing

June 1988

679 pages

ISBN:0897912721

DOI:10.1145/55364

Editor:
J. Lenfant
Rennes

Copyright © 1988 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1988

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Chang JHerrero ECanal RSohi G(2011)Cooperative Caching for Chip MultiprocessorsCooperative Networking10.1002/9781119973584.ch13(217-275)Online publication date: 13-Jul-2011
https://doi.org/10.1002/9781119973584.ch13
Chapman MHeiser G(2009)vNUMAProceedings of the 2009 conference on USENIX Annual technical conference10.5555/1855807.1855809(2-2)Online publication date: 14-Jun-2009
https://dl.acm.org/doi/10.5555/1855807.1855809
Chtioui HAtitallah RNiar SDekeyser JAbid M(2009)A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.220(3-10)Online publication date: 27-Aug-2009
https://dl.acm.org/doi/10.1109/DSD.2009.220
Rothman JSmith A(2009)MinervaProceedings of the 4th International Symposium on High Performance Computing10.1007/3-540-47847-7_8(64-77)Online publication date: 18-May-2009
https://dl.acm.org/doi/10.1007/3-540-47847-7_8
Chang JSohi G(2006)Cooperative Caching for Chip MultiprocessorsACM SIGARCH Computer Architecture News10.1145/1150019.113650934:2(264-276)Online publication date: 1-May-2006
https://dl.acm.org/doi/10.1145/1150019.1136509
Chang JSohi G(2006)Cooperative Caching for Chip MultiprocessorsProceedings of the 33rd annual international symposium on Computer Architecture10.1109/ISCA.2006.17(264-276)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1109/ISCA.2006.17
Tao JSchulz MKarl W(2005)Simulation as a tool for optimizing memory accesses on NUMA machinesPerformance Evaluation10.1016/j.peva.2004.10.00360:1-4(31-50)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1016/j.peva.2004.10.003
Tao JKarl W(2004)Impact of Cache Coherence Models on Performance of OpenMP ApplicationsEuro-Par 2004 Parallel Processing10.1007/978-3-540-27866-5_19(149-154)Online publication date: 2004
https://doi.org/10.1007/978-3-540-27866-5_19
Mu TTao JSchulz MMcKee SDiehl SStasko J(2003)Interactive locality optimization on NUMA architecturesProceedings of the 2003 ACM symposium on Software visualization10.1145/774833.774853(133-ff)Online publication date: 11-Jun-2003
https://dl.acm.org/doi/10.1145/774833.774853
Benc IStefanec MSrbljic S(2001)Decision function in hybrid self-adaptive WWW cache coherence protocol (hSATTL)EUROCON'2001. International Conference on Trends in Communications. Technical Program, Proceedings (Cat. No.01EX439)10.1109/EURCON.2001.938119(301-304)Online publication date: 2001
https://doi.org/10.1109/EURCON.2001.938119
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