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Comparative analysis of OpenCL and RTL for sort-merge primitives on FPGA

Published: 14 June 2020 Publication History

Abstract

As a result of recent improvements in FPGA technology, their benefits for highly efficient data processing pipelines are becoming more and more apparent. However, traditional RTL methods for programming FPGAs require knowledge of digital design and hardware description languages. OpenCL provides software developers with a C-based platform for implementing their applications without deep knowledge of digital design. In this paper, we conduct a comparative analysis of OpenCL and RTL-based implementations of a novel heapsort with merging sorted runs. In particular, we quantitatively compare their performance, FPGA resource utilization, and development effort. Our results show that while requiring comparable development effort, RTL implementations of critical primitives used in the algorithm achieve 4X better performance while using half as much the FPGA resources.

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  • (2024)ArcaDB: A Disaggregated Query Engine for Heterogenous Computational Environments2024 IEEE 17th International Conference on Cloud Computing (CLOUD)10.1109/CLOUD62652.2024.00015(42-53)Online publication date: 7-Jul-2024
  • (2023)KeRRaS: Sort-Based Database Query Processing on Wide Tables Using FPGAsProceedings of the 19th International Workshop on Data Management on New Hardware10.1145/3592980.3595300(1-9)Online publication date: 18-Jun-2023
  • (2023)Out-of-the-box library support for DBMS operations on GPUsDistributed and Parallel Databases10.1007/s10619-023-07431-341:3(489-509)Online publication date: 10-May-2023
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cover image ACM Conferences
DaMoN '20: Proceedings of the 16th International Workshop on Data Management on New Hardware
June 2020
127 pages
ISBN:9781450380249
DOI:10.1145/3399666
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 14 June 2020

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Author Tags

  1. FPGA
  2. Intel® OpenCL
  3. RTL
  4. external sorting
  5. heapsort
  6. high level synthesis
  7. sorting

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DaMoN '20 Paper Acceptance Rate 18 of 22 submissions, 82%;
Overall Acceptance Rate 94 of 127 submissions, 74%

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Cited By

View all
  • (2024)ArcaDB: A Disaggregated Query Engine for Heterogenous Computational Environments2024 IEEE 17th International Conference on Cloud Computing (CLOUD)10.1109/CLOUD62652.2024.00015(42-53)Online publication date: 7-Jul-2024
  • (2023)KeRRaS: Sort-Based Database Query Processing on Wide Tables Using FPGAsProceedings of the 19th International Workshop on Data Management on New Hardware10.1145/3592980.3595300(1-9)Online publication date: 18-Jun-2023
  • (2023)Out-of-the-box library support for DBMS operations on GPUsDistributed and Parallel Databases10.1007/s10619-023-07431-341:3(489-509)Online publication date: 10-May-2023
  • (2022)An Open-source FPGA Library for Data SortingJournal of Information Processing10.2197/ipsjjip.30.76630(766-777)Online publication date: 2022
  • (2022)NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSDACM Transactions on Reconfigurable Technology and Systems10.1145/347276915:2(1-29)Online publication date: 30-Jun-2022
  • (2021)Analysis of GPU-Libraries for Rapid Prototyping Database Operations : A look into library support for database operations2021 IEEE 37th International Conference on Data Engineering Workshops (ICDEW)10.1109/ICDEW53142.2021.00014(36-41)Online publication date: Apr-2021

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