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Parameterized system design

Published: 01 May 2000 Publication History

Abstract

Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To be used across a variety of applications, such architectures must be heavily parameterized, so they can adapt to those applications' differing constraints by trading off power, performance and size. We describe several parameterized system design issues, and provide results showing how a single architecture with easily configurable parameters can support a wide range of tradeoffs.

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Published In

cover image ACM Conferences
CODES '00: Proceedings of the eighth international workshop on Hardware/software codesign
May 2000
167 pages
ISBN:1581132689
DOI:10.1145/334012
  • Chairmen:
  • Frank Vahid,
  • Jan Madsen
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 May 2000

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Author Tags

  1. cache
  2. estimation
  3. intellectual property
  4. low power
  5. on-chip bus
  6. system parameters
  7. system-on-a-chip

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Cited By

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  • (2010)Automatic generation of a parameter-domain-based functional input coverage model2010 11th Latin American Test Workshop10.1109/LATW.2010.5550344(1-6)Online publication date: Mar-2010
  • (2010)Parameterized bus interface design based on Verilog language2010 International Conference on Computer Application and System Modeling (ICCASM 2010)10.1109/ICCASM.2010.5619344(V8-185-V8-187)Online publication date: Oct-2010
  • (2010)Communication architecture design for reconfigurable multimedia SoC platformDesign Automation for Embedded Systems10.1007/s10617-009-9048-014:1(1-20)Online publication date: 1-Mar-2010
  • (2008)Design and verification of the programming circuit in an application-specific FPGA2008 9th International Conference on Solid-State and Integrated-Circuit Technology10.1109/ICSICT.2008.4734975(2047-2050)Online publication date: Oct-2008
  • (2008)Automatic generation of random stimuli sources based on Parameter Domains for functional verification2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software10.1109/DCAS.2008.4695923(1-4)Online publication date: Oct-2008
  • (2007)Optimal allocation of I/O device parameters in hardware and software codesign methodologyProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780804(541-552)Online publication date: 17-Dec-2007
  • (2007)Families of FPGA-based accelerators for approximate string matchingMicroprocessors & Microsystems10.1016/j.micpro.2006.04.00131:2(135-145)Online publication date: 1-Mar-2007
  • (2007)Efficient architecture/compiler co-exploration using analytical modelsDesign Automation for Embedded Systems10.1007/s10617-006-9588-711:1(1-23)Online publication date: 1-Mar-2007
  • (2007)Optimal Allocation of I/O Device Parameters in Hardware and Software Codesign MethodologyEmbedded and Ubiquitous Computing10.1007/978-3-540-77092-3_47(541-552)Online publication date: 2007
  • (2006)A highly parameterizable parallel processor array architecture2006 IEEE International Conference on Field Programmable Technology10.1109/FPT.2006.270293(105-112)Online publication date: Dec-2006
  • Show More Cited By

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