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SMURF: Scalar Multiple-precision Unum Risc-V Floating-point Accelerator for Scientific Computing

Published: 13 March 2019 Publication History

Abstract

This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

References

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A. Bocco, Y. Durand, and F. de Dinechin. 2017. Hardware support for UNUM floating point arithmetic. In Ph.D. Research in Microelectronics and Electronics. 93--96.
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Cohen, Hull, and Hamacher. 1983. CADAC: A Controlled-Precision Decimal Arithmetic Unit. IEEE Trans. Comput. C-32, 4 (April 1983), 370--377.
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Asanović Krste et al. 2016. The Rocket Chip Generator. Technical Report UCB/EECS-2016-17. EECS Department, University of California, Berkeley. http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html
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Laurent Fousse, Guillaume Hanrot, Vincent Lefèvre, Patrick Pélissier, and Paul Zimmermann. 2007. MPFR: A Multiple-precision Binary Floating-point Library with Correct Rounding. ACM Trans. Math. Softw. 33, 2, Article 13 (June 2007).
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F. Glaser, S. Mach, A. Rahimi, F. K. Gürkaynak, Q. Huang, and L. Benini. 2018. An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. In International Symposium on Circuits and Systems. 1--5.
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Torbjörn Granlund and the GMP development team. 2012. GNU MP: The GNU Multiple Precision Arithmetic Library. https://gmplib.org/ Version 5.0.5.
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John L. Gustafson. 2015. The End of Error: Unum Computing. Chapman and Hall/CRC.
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J. Hou, Y. Zhu, Y. Shen, M. Li, H. Wu, and H. Song. 2017. Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic Implementation on FPGA. In High Performance Computing and Communications. 615--616.
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T. E. Hull, M. S. Cohen, and C. B. Hall. 1991. Specifications for a variable-precision arithmetic coprocessor. In Proceedings 10th IEEE Symposium on Computer Arithmetic. 127--131.
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IEEE754-2008 2008. IEEE Standard for Floating-Point Arithmetic. IEEE 754--2008, also ISO/IEC/IEEE 60559:2011.
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Ulirich Kulisch. 2013. Computer arithmetic and validity: Theory, implementation, and applications, 2nd edition. De Gruyter.
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Anuj Rao. {n. d.}. The RoCC Doc V2: An Introduction to the Rocket Custom Coprocessor Interface. ({n. d.}). https://docs.google.com/document/d/1CH2ep4YcL_ojsa3BVHEW-uwcKh1FlFTjH_kg5v8bxVw
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M. J. Schulte and E. E. Swartzlander. 2000. A family of variable-precision interval arithmetic processors. IEEE Trans. Comput. 49, 5 (May 2000), 387--397.

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  • (2024)Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point ComputationIEEE Transactions on Computers10.1109/TC.2024.338396473:7(1683-1697)Online publication date: 2-Apr-2024
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cover image ACM Other conferences
CoNGA'19: Proceedings of the Conference for Next Generation Arithmetic 2019
March 2019
66 pages
ISBN:9781450371391
DOI:10.1145/3316279
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 March 2019

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Author Tags

  1. ASIC
  2. Coprocessor
  3. FPGA
  4. Floating-point
  5. Hardware architecture
  6. Instruction set design
  7. Multiple precision
  8. RISC-V
  9. Scientific computing
  10. UNUM
  11. Variable precision

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  • Research-article
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  • Refereed limited

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CoNGA'19
CoNGA'19: Conference for Next Generation Arithmetic 2019
March 13 - 14, 2019
Singapore, Singapore

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Cited By

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  • (2024)Accelerating Spectral Elements Method with Extended Precision: A Case StudyInternational Journal of Applied Physics and Mathematics10.17706/ijapm.2024.14.2.45-5814:2(45-58)Online publication date: 2024
  • (2024)SPADIX: A Highly Efficient Accelerator for Solving 3-D Partial Differential EquationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338261443:9(2797-2809)Online publication date: Sep-2024
  • (2024)Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point ComputationIEEE Transactions on Computers10.1109/TC.2024.338396473:7(1683-1697)Online publication date: 2-Apr-2024
  • (2024)A Variable and Extended Precision (VRP) Accelerator and its 22 nm SoC Implementation2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS62603.2024.10769136(1-6)Online publication date: 13-Nov-2024
  • (2024)Implementation of Neural Network using Posit Arithmetic Circuits2023 4th International Conference on Intelligent Technologies (CONIT)10.1109/CONIT61985.2024.10627298(1-5)Online publication date: 21-Jun-2024
  • (2022)A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data AnalyticsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.310176433:5(1038-1053)Online publication date: 1-May-2022
  • (2022)Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00016(57-72)Online publication date: Oct-2022
  • (2022)Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor2022 IEEE 29th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH54963.2022.00017(51-57)Online publication date: Sep-2022
  • (2022)Cost-effective fixed-point hardware support for RISC-V embedded systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102476126:COnline publication date: 23-May-2022
  • (2022)On the Implementation of Edge Detection Algorithms with SORN ArithmeticNext Generation Arithmetic10.1007/978-3-031-09779-9_1(1-13)Online publication date: 14-Jul-2022
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