research-article

Public Access

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs

Authors:

Ayse K. Coskun,

Vasilis F. Pavlidis,

Emre SalmanAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 439 - 444

https://doi.org/10.1145/3299874.3319485

Published: 13 May 2019 Publication History

Abstract

Monolithic 3D (Mono3D) is a three-dimensional integration technology that can overcome some of the fundamental limitations faced by traditional, two-dimensional scaling. This paper analyzes the unique thermal characteristics of Mono3D ICs by simulating a two-tier flip-chip Mono3D IC and highlights the primary differences in comparison to a similarly-sized flip-chip TSV-based 3D IC. Specifically, we perform architectural-level thermal simulations for both technologies and demonstrate that vertical thermal coupling is stronger in Mono3D ICs, leading to lower upper tier temperatures. We also investigate the significance of lateral versus vertical flow of heat in Mono3D ICs. We simulate different hot spot scenarios in a two-tier Mono3D IC and show that although the lateral heat flow is limited as compared to TSV-based 3D ICs, ignoring this mechanism can cause nonnegligible error (~4°C) in temperature estimation, particularly for layers farther from the heat sink. In addition, we show that with increasing interconnect utilization (due to the contribution of Joule heating to overall temperature), the on-chip temperatures and the significance of lateral heat flow within the two-tier Mono3D IC also increase. Finally, we discuss potential opportunities in Mono3D ICs to enhance their thermal integrity.

References

[1]

Why Monolithic 3D? http://www.monolithic3d.com/why-monolithic-3d.html

[2]

P. Batude et al. 2008. Enabling 3D Monolithic Integration. ECS Transactions 16, 8 (2008), 47--54.

[3]

P. Batude et al. 2009. GeOI and SOI 3D monolithic cell integrations for high density applications. In IEEE Symposium on VLSI Technology. 166--167.

[4]

P. Batude et al. 2014. 3D sequential integration opportunities and technology optimization. In IEEE Proc. of International Interconnect Technology Conference. 373--376.

[5]

P. Batude et al. 2015. 3DVLSI with CoolCube process: An alternative path to scaling. In IEEE Symposium on VLSI Technology. T48--T49.

[6]

G. Berhault et al. 2016. 3DIP: An iterative partitioning tool for monolithic 3D IC. In IEEE Proc. of International 3D Systems Integration Conference (3DIC). 1--5.

[7]

A. Guler and N. K. Jha. 2018. Hybrid monolithic 3D IC floorplanner. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 10 (Oct. 2018), 1868--1880.

[8]

R. Ho, K.W. Mai, and M. A. Horowitz. 2001. The future of wires. Proc. of the IEEE 89, 4 (2001), 490--504.

[9]

M. A. Iqbal and M. Rahman. 2017. New thermal management approach for transistor-level 3-D integtration. In IEEE Proc. of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--3.

[10]

K. M. Kim et al. 2016. Four-tier monolithic 3D ICs: Tier partitioning methodology and power benefit study. In ACM Proc. of International Symposium on Low Power Electronics and Design (ISLPED). 70--75.

Digital Library

[11]

J. Meng, K. Kawakami, and A. K. Coskun. 2012. Optimizing energy efficiency of 3D multicore systems with stacked DRAM under power and thermal constraints. In ACM Proc. of Design Automation Conference (DAC). 648--655.

Digital Library

[12]

Z. Or-Bach. 2013. The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7 x scaling. In IEEE Proc. of the International 3D Systems Integration Conference (3DIC). 1--7.

[13]

S. Panth, K. Samadi, Y. Du, and S. K. Lim. 2015. Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 4 (Apr. 2015), 540--553.

Digital Library

[14]

G. Pares et al. 2011. Through silicon via technology using tungsten metallization. In IEEE Proc. of International Conference on IC Design & Technology. 1--4.

[15]

V. F. Pavlidis, I. Savidis, and E. G. Friedman. 2017. Three-dimensional integrated circuit design. Newnes.

Digital Library

[16]

I. Pletea, Z.Wurman, Z. Or-Bach, and V. Sontea. 2015. Monolithic 3D layout using 2D EDA for embedded memory-rich designs. In IEEE Proc. of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--2.

[17]

S. K. Samal et al. 2014. Full chip impact study of power delivery network designs in monolithic 3D ICs. In IEEE/ACM Proc. of International Conference on Computer-Aided Design (ICCAD). 565--572.

Digital Library

[18]

S. K. Samal et al. 2016. Adaptive regression-based thermal modeling and optimization for monolithic 3D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, 10 (Oct. 2016), 1707--1720.

Digital Library

[19]

S. K. Samal et al. 2016. Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs. In ACM Proc. of International Conference on Computer-Aided Design (ICCAD). 129.

Digital Library

[20]

S. M. Satheesh and E. Salman. 2012. Power distribution in TSV-based 3D processormemory stacks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, 4 (Dec. 2012), 692--703.

[21]

M. Schultz et al. 2016. Embedded two-phase cooling of large three-dimensional compatible chips with radial channels. Journal of Electronic Packaging 138, 2 (Apr. 2016), 021005.

[22]

K. Skadron et al. 2003. Temperature-aware microarchitecture. In IEEE Proc. of International Symposium on Computer Architecture (ISCA). 2--13.

Digital Library

[23]

G. J. Snyder et al. 2006. Hot spot cooling using embedded thermoelectric coolers. In IEEE Semiconductor Thermal Measurement And Management Symposium. 135--143.

[24]

H. Wei et al. 2012. Cooling three-dimensional integrated circuits using power delivery networks. In IEEE International Electron Devices Meeting. 14--2.

[25]

Q. Xie et al. 2015. Performance comparisons between 7-nm FinFET and conventional bulk CMOS standard cell libraries. IEEE Transactions on Circuits and Systems II: Express Briefs 62, 8 (Aug. 2015), 761--765.

[26]

C. Yan, S. Kontak, H. Wang, and E. Salman. 2017. Open source cell library Mono3D to develop large-scale monolithic 3D integrated circuits. In IEEE Proc. of International Symposium on Circuits and Systems. 1--4.

[27]

C. Yan and E. Salman. 2017. Routing congestion aware cell Library development for monolithic 3D ICs. In International Conference on Rebooting Computing. 1--4.

[28]

C. Yan and E. Salman. 2018. Mono3D: Open source cell library for monolithic 3D integrated circuits. IEEE Transactions on Circuits and Systems I: Regular Papers 65, 3 (Mar. 2018), 1075--1085.

Cited By

Chen YSankatali VMishra SRyckaert JMyers JBiswas D(2024)Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00020(45-50)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00020
Wang QZhu TLin YWang RHuang R(2024)ATSim3D: Towards Accurate Thermal Simulator for Heterogeneous 3D-IC Systems Considering Nonlinear Leakage and Conductivity2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617604(618-623)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617604
Kumar SChauhan YAmrouch H(2024)Monolithic 3D Integration using BEOL FeFET: Reliability, Thermal Effects, and DNN Accuracy2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)10.1109/EDTM58488.2024.10511909(1-3)Online publication date: 3-Mar-2024
https://doi.org/10.1109/EDTM58488.2024.10511909
Show More Cited By

Index Terms

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs
1. Hardware
  1. Integrated circuits
    1. 3D integrated circuits
    2. Interconnect
  2. Power and energy
    1. Thermal issues
      1. Temperature simulation and estimation

Recommendations

Design and CAD methodologies for low power gate-level monolithic 3D ICs
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-...
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs
DAC '14: Proceedings of the 51st Annual Design Automation Conference

In this paper, we present a comprehensive study of the unique thermal behavior in monolithic 3D ICs. In particular, we study the impact of the thin inter-layer dielectric (ILD) between the device tiers on vertical thermal coupling. In addition, we ...
Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 May 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

National Science Foundation

Conference

GLSVLSI '19

Sponsor:

SIGDA

GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

23
Total Citations
View Citations
1,414
Total Downloads

Downloads (Last 12 months)518
Downloads (Last 6 weeks)80

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chen YSankatali VMishra SRyckaert JMyers JBiswas D(2024)Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00020(45-50)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00020
Wang QZhu TLin YWang RHuang R(2024)ATSim3D: Towards Accurate Thermal Simulator for Heterogeneous 3D-IC Systems Considering Nonlinear Leakage and Conductivity2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617604(618-623)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617604
Kumar SChauhan YAmrouch H(2024)Monolithic 3D Integration using BEOL FeFET: Reliability, Thermal Effects, and DNN Accuracy2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)10.1109/EDTM58488.2024.10511909(1-3)Online publication date: 3-Mar-2024
https://doi.org/10.1109/EDTM58488.2024.10511909
Jayachandran DPendurthi RSadaf MSakib NPannone AChen CHan YTrainor NKumari SMc Knight TRedwing JYang YDas S(2024)Three-dimensional integration of two-dimensional field-effect transistorsNature10.1038/s41586-023-06860-5625:7994(276-281)Online publication date: 10-Jan-2024
https://doi.org/10.1038/s41586-023-06860-5
Lin ZLi JSun ZFang AHan KJia SLiu YAdams MMoon KWong C(2024)Facile Chemical Surface Modification of Boron Nitride Platelets and Improved Thermal and Mechanical Properties of Their Polymer Compounds for 2.5D/3D Packaging ApplicationsComposites Science and Technology10.1016/j.compscitech.2024.110778(110778)Online publication date: Jul-2024
https://doi.org/10.1016/j.compscitech.2024.110778
Miketic IDhananjay KSalman E(2023)Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated SystemsSensors10.3390/s2304208123:4(2081)Online publication date: 13-Feb-2023
https://doi.org/10.3390/s23042081
Srimani TRadway RKim JPrabhu KRich DGilardi CRaina PShulaker MLim SMitra S(2023)Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137051(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137051
Shukla PPavlidis VSalman ECoskun A(2023)TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328503942:12(4350-4363)Online publication date: 12-Jun-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3285039
Abdurrob ASalman ELombardi J(2023)Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators2023 IEEE 36th International System-on-Chip Conference (SOCC)10.1109/SOCC58585.2023.10256927(1-6)Online publication date: 5-Sep-2023
https://doi.org/10.1109/SOCC58585.2023.10256927
Köroğlu ÇPop E(2023)High Thermal Conductivity Insulators for Thermal Management in 3D Integrated CircuitsIEEE Electron Device Letters10.1109/LED.2023.324067644:3(496-499)Online publication date: Mar-2023
https://doi.org/10.1109/LED.2023.3240676
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents