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FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks

Authors:

Michaela Blott,

Thomas B. Preußer,

Nicholas J. Fraser,

Giulio Gambardella,

Kenneth O’brien,

Yaman Umuroglu,

Kees VissersAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 11, Issue 3

Article No.: 16, Pages 1 - 23

https://doi.org/10.1145/3242897

Published: 15 December 2018 Publication History

Abstract

Convolutional Neural Networks have rapidly become the most successful machine-learning algorithm, enabling ubiquitous machine vision and intelligent decisions on even embedded computing systems. While the underlying arithmetic is structurally simple, compute and memory requirements are challenging. One of the promising opportunities is leveraging reduced-precision representations for inputs, activations, and model parameters. The resulting scalability in performance, power efficiency, and storage footprint provides interesting design compromises in exchange for a small reduction in accuracy. FPGAs are ideal for exploiting low-precision inference engines leveraging custom precisions to achieve the required numerical accuracy for a given application. In this article, we describe the second generation of the FINN framework, an end-to-end tool that enables design-space exploration and automates the creation of fully customized inference engines on FPGAs. Given a neural network description, the tool optimizes for given platforms, design targets, and a specific precision. We introduce formalizations of resource cost functions and performance predictions and elaborate on the optimization algorithms. Finally, we evaluate a selection of reduced precision neural networks ranging from CIFAR-10 classifiers to YOLO-based object detection on a range of platforms including PYNQ and AWS F1, demonstrating new unprecedented measured throughput at 50 TOp/s on AWS F1 and 5 TOp/s on embedded devices.

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Index Terms

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 11, Issue 3

Special Issue on Deep learning on FPGAs

September 2018

187 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3299999

Editor:
Steve Wilton
Department of Electrical and Computer Engineering / University of British Columbia / Kaiser 4112, 5500-2332 Main Mall / Vancouver, BC V6T 1Z4 Canada

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Publication History

Published: 15 December 2018

Accepted: 01 July 2018

Revised: 01 April 2018

Received: 01 December 2017

Published in TRETS Volume 11, Issue 3

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Jiang YVaicaitis ADooley JLeeser M(2024)Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation FunctionSensors10.3390/s2406182924:6(1829)Online publication date: 13-Mar-2024
https://doi.org/10.3390/s24061829
Wan RCen RZhang DWang D(2024)LDF-BNN: A Real-Time and High-Accuracy Binary Neural Network Accelerator Based on the Improved BNextMicromachines10.3390/mi1510126515:10(1265)Online publication date: 17-Oct-2024
https://doi.org/10.3390/mi15101265
Su YSeng KSmith JAng L(2024)Efficient FPGA Binary Neural Network Architecture for Image Super-ResolutionElectronics10.3390/electronics1302026613:2(266)Online publication date: 6-Jan-2024
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