research-article

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

Authors:

Srivatsa Srinivasa,

Akshay Krishna Ramanathan,

Chih-Chao Yang,

Chang-Hong Shen,

Meng-Fan Marvin Chang,

Vijaykrishnan NarayananAuthors Info & Claims

ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design

Article No.: 34, Pages 1 - 6

https://doi.org/10.1145/3218603.3218645

Published: 23 July 2018 Publication History

Abstract

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed two-layer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

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Cited By

Do CKim CChung S(2022)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 21-Oct-2022
https://doi.org/10.1007/s11227-022-04878-6
Lee EKim DKim JLim SMukhopadhyay S(2021)A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube ProcessACM Journal on Emerging Technologies in Computing Systems10.1145/346668118:1(1-20)Online publication date: 3-Nov-2021
https://dl.acm.org/doi/10.1145/3466681
GONG YKONG JCHUNG S(2021)Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 CachesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2019.28949829:2(854-865)Online publication date: 1-Apr-2021
https://doi.org/10.1109/TETC.2019.2894982
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Index Terms

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support
1. Hardware
  1. Integrated circuits
    1. 3D integrated circuits

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cover image ACM Conferences

ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design

July 2018

327 pages

ISBN:9781450357043

DOI:10.1145/3218603

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 July 2018

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SIGDA

ISLPED '18: International Symposium on Low Power Electronics and Design

July 23 - 25, 2018

WA, Seattle, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Do CKim CChung S(2022)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 21-Oct-2022
https://doi.org/10.1007/s11227-022-04878-6
Lee EKim DKim JLim SMukhopadhyay S(2021)A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube ProcessACM Journal on Emerging Technologies in Computing Systems10.1145/346668118:1(1-20)Online publication date: 3-Nov-2021
https://dl.acm.org/doi/10.1145/3466681
GONG YKONG JCHUNG S(2021)Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 CachesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2019.28949829:2(854-865)Online publication date: 1-Apr-2021
https://doi.org/10.1109/TETC.2019.2894982
Liao HTu JXia JLiu HZhou XYuan HHu Y(2021)Ascend: a Scalable and Unified Architecture for Ubiquitous Deep Neural Network Computing : Industry Track Paper2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00071(789-801)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00071
Mittal SVerma GKaushik BKhanday F(2021)A survey of SRAM-based in-memory computing techniques and applicationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102276119:COnline publication date: 1-Oct-2021
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102276
Wang FLi JZhang ZDing YXiong YHou XChen HZhou P(2021)Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistorsiScience10.1016/j.isci.2021.10313824:10(103138)Online publication date: Oct-2021
https://doi.org/10.1016/j.isci.2021.103138
Simon WQureshi YRios MLevisse AZapater MAtienza D(2020)BLADE: An in-Cache Computing Architecture for Edge DevicesIEEE Transactions on Computers10.1109/TC.2020.297252869:9(1349-1363)Online publication date: 1-Sep-2020
https://doi.org/10.1109/TC.2020.2972528
Zokaee FZhang MYe XFan DJiang L(2019)MagmaProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317858(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317858
Gopireddy BTorrellas JManne SHunter HAltman E(2019)Designing vertical processors in monolithic 3DProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322233(643-656)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322233
Jao NSrivinasa SRamanathan AKim MSampson JNarayanan V(2019)Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)10.1109/NANOARCH47378.2019.181303(1-6)Online publication date: Jul-2019
https://doi.org/10.1109/NANOARCH47378.2019.181303
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