research-article

Reducing time and effort in IC implementation: a roadmap of challenges and solutions

Author:

Andrew B. KahngAuthors Info & Claims

DAC '18: Proceedings of the 55th Annual Design Automation Conference

Article No.: 36, Pages 1 - 6

https://doi.org/10.1145/3195970.3199854

Published: 24 June 2018 Publication History

Abstract

To reduce time and effort in IC implementation, fundamental challenges must be solved. First, the need for (expensive) humans must be removed wherever possible. Humans are skilled at predicting downstream flow failures, evaluating key early decisions such as RTL floorplanning, and deciding tool/flow options to apply to a given design. Achieving human-quality prediction, evaluation and decision-making will require new machine learning-centric models of both tools and designs. Second, to reduce design schedule, focus must return to the long-held dream of single-pass design. Future design tools and flows that never require iteration (i.e., that never fail, but without undue conservatism) demand new paradigms and core algorithms for parallel, cloud-based design automation. Third, learning-based models of tools and flows must continually improve with additional design experiences. Therefore, the EDA and design ecosystem must develop new infrastructure for ML model development and sharing.

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Karimullah SVishnuvardhan DGunjan VShaik F(2024)Optimization of Area and Wirelength Using Hybrid BPSO Algorithm in VLSI Floorplan and Placement for IC DesignModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-031-43009-1_11(121-130)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-43009-1_11
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https://doi.org/10.3390/electronics11071161
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cover image ACM Conferences

DAC '18: Proceedings of the 55th Annual Design Automation Conference

June 2018

1089 pages

ISBN:9781450357005

DOI:10.1145/3195970

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 24 June 2018

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Cited By

Karimullah SVishnuvardhan DGunjan VShaik F(2024)Optimization of Area and Wirelength Using Hybrid BPSO Algorithm in VLSI Floorplan and Placement for IC DesignModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-031-43009-1_11(121-130)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-43009-1_11
Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Islam R(2022)Feasibility Prediction for Rapid IC Design Space ExplorationElectronics10.3390/electronics1107116111:7(1161)Online publication date: 6-Apr-2022
https://doi.org/10.3390/electronics11071161
Mirhoseini AGoldie AYazgan MJiang JSonghori EWang SLee YJohnson EPathak ONova APak JTong ASrinivasa KHang WTuncer ELe QLaudon JHo RCarpenter RDean J(2021)A graph placement methodology for fast chip designNature10.1038/s41586-021-03544-w594:7862(207-212)Online publication date: 9-Jun-2021
https://doi.org/10.1038/s41586-021-03544-w
Ansell TSaligane MXie Y(2020)The missing pieces of open design enablementProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415736(1-8)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415736
Kahng ASchlichtmann UGal RAmrouch HLi H(2020)MLCAD Today and Tomorrow: Learning, Optimization and ScalingProceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3380446.3430685(1-1)Online publication date: 16-Nov-2020
https://dl.acm.org/doi/10.1145/3380446.3430685
Mangalagiri PBustany ISwartz W(2019)Analog Layout SynthesisProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3311065(127-127)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3299902.3311065
Fogaça MKahng AReis RWang LShibuya T(2019)Finding placement-relevant clusters with fast modularity-based clusteringProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287676(569-576)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287676
Kahng A(2019)Looking Into the Mirror of Open Source: Invited Paper2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942131(1-8)Online publication date: Nov-2019
https://doi.org/10.1109/ICCAD45719.2019.8942131
Nier TGao JZhou L(2019)Constraint propagation in physical design of circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2019.0342Online publication date: 28-Oct-2019
https://doi.org/10.1049/iet-cds.2019.0342

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