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Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

Authors:

Nitish Srivastava,

Joseph Featherston,

Gustavo Angarita Velasquez,

Zhiru ZhangAuthors Info & Claims

FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 269 - 278

https://doi.org/10.1145/3174243.3174255

Published: 15 February 2018 Publication History

Abstract

Modern high-level synthesis (HLS) tools greatly reduce the turn-around time of designing and implementing complex FPGA-based accelerators. They also expose various optimization opportunities, which cannot be easily explored at the register-transfer level. With the increasing adoption of the HLS design methodology and continued advances of synthesis optimization, there is a growing need for realistic benchmarks to (1) facilitate comparisons between tools, (2) evaluate and stress-test new synthesis techniques, and (3) establish meaningful performance baselines to track progress of the HLS technology. While several HLS benchmark suites already exist, they are primarily comprised of small textbook-style function kernels, instead of complete and complex applications. To address this limitation, we introduce Rosetta, a realistic benchmark suite for software programmable FPGAs. Designs in Rosetta are fully-developed applications. They are associated with realistic performance constraints, and optimized with advanced features of modern HLS tools. We believe that Rosetta is not only useful for the HLS research community, but can also serve as a set of design tutorials for non-expert HLS users. In this paper we describe the characteristics of our benchmarks and the optimization techniques applied to them. We further report experimental results on an embedded FPGA device as well as a cloud FPGA platform.

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Cited By

Abi-Karam SSarkar RSeigler ALowe SWei ZChen HRao NJohn LArora AHao CAmrouch HHu JGarg SLin Y(2024)HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685961(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685961
Du LLiang TZhou XGe JLi SSinha SZhao JXie ZZhang W(2024)FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/365345817:3(1-33)Online publication date: 20-Mar-2024
https://dl.acm.org/doi/10.1145/3653458
Santos TBispo JCardoso JShrivastava ASui Y(2024)A Flexible-Granularity Task Graph Representation and Its Generation from C Applications (WIP)Proceedings of the 25th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3652032.3657580(178-182)Online publication date: 20-Jun-2024
https://dl.acm.org/doi/10.1145/3652032.3657580
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Index Terms

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
      2. Reconfigurable computing
2. Hardware
  1. Electronic design automation

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cover image ACM Conferences

FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2018

310 pages

ISBN:9781450356145

DOI:10.1145/3174243

General Chair:
Jason H. Anderson
University of Toronto, Canada
,
Program Chair:
Kia Bazargan
University of Minnesota, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 15 February 2018

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National Science Foundation
Defense Advanced Research Projects Agency

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FPGA '18

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SIGDA

FPGA '18: The 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 25 - 27, 2018

CALIFORNIA, Monterey, USA

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FPGA '18 Paper Acceptance Rate 10 of 116 submissions, 9%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Abi-Karam SSarkar RSeigler ALowe SWei ZChen HRao NJohn LArora AHao CAmrouch HHu JGarg SLin Y(2024)HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685961(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685961
Du LLiang TZhou XGe JLi SSinha SZhao JXie ZZhang W(2024)FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/365345817:3(1-33)Online publication date: 20-Mar-2024
https://dl.acm.org/doi/10.1145/3653458
Santos TBispo JCardoso JShrivastava ASui Y(2024)A Flexible-Granularity Task Graph Representation and Its Generation from C Applications (WIP)Proceedings of the 25th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3652032.3657580(178-182)Online publication date: 20-Jun-2024
https://dl.acm.org/doi/10.1145/3652032.3657580
Wong LZhang JLi J(2024)DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLSACM Transactions on Reconfigurable Technology and Systems10.1145/365003817:3(1-32)Online publication date: 5-Mar-2024
https://dl.acm.org/doi/10.1145/3650038
Liao YAdegbija TLysecky RTandon R(2024)Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine LearningProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658738(170-176)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658738
Miliadis PTheodoropoulos DPnevmatikatos DKoziris N(2024)Architectural Support for Sharing, Isolating and Virtualizing FPGA ResourcesACM Transactions on Architecture and Code Optimization10.1145/364847521:2(1-26)Online publication date: 21-May-2024
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Gorius JRokicki SDerrien SRodríguez GSadayappan PSukumaran-Rajam A(2024)A Unified Memory Dependency Framework for Speculative High-Level SynthesisProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641581(13-25)Online publication date: 17-Feb-2024
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Park DDeHon AZhang ZPutnam A(2024)REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA DesignsProceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3626202.3637560(108-118)Online publication date: 1-Apr-2024
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Liang TChen GZhao JSinha SZhang W(2024)AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337335743:9(2769-2782)Online publication date: Sep-2024
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Wan LHuang YLi YYe HWang JZhang XChen D(2024)Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473893(435-441)Online publication date: 22-Jan-2024
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