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An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Authors:

Takeshi OguraAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 10 - es

https://doi.org/10.1145/307418.307445

Published: 01 January 1999 Publication History

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References

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{6} M. Mizuno et al., "A 1.5W Single-Chip MPEG-2 MP@ML Video Encoder,.," IEEE J. Solid-State Circuits, vol. 32, pp. 1807-1816, November 1997.

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{7} E. Miyagoshi et al., "A 100mm² 0.95W Single-Chip MPEG2 MP@ML Video Encoder,.," Proc. of the International Solid-State Circuits Conference, pp. 30- 31, February 1998.

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{8} E. Ogura et al., "A 1.2W Single-Chip MPEG2 MP@ML Video Encoder LSI,.," Proc. of the International Solid-State Circuits Conference, pp. 32-33, February 1998.

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{9} T. Minami et al. "A Single-chip MPEG2 MP@ML Video Encoder LSI with Multi-chip Configuration for a Single-board MP@HL Encoder," Symposium HOT Chips X, August 1998.

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{10} K. Ochiai et al. "High-speed Software-based Platform for Embedded Software of a Single-chip MPEG- 2 Video Encoder LSI with HDTV Scalability," Proc. of the Design, Automation and Test in Europe (DATE99), March 1999.

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Cited By

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NAKAMURA KOMORI YKOBAYASHI DNITTA KSANO KSATO MIWASAKI HKOBAYASHI H(2023)An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding ArchitectureIEICE Transactions on Electronics10.1587/transele.2022LHP0002E106.C:6(312-320)Online publication date: 1-Jun-2023
https://doi.org/10.1587/transele.2022LHP0002
Yoshitome TNakamura KKamikura K(2010)A Flexible Super High Resolution Video CODEC and Its Trial ExperimentsHigh-Quality Visual Experience10.1007/978-3-642-12802-8_7(177-195)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12802-8_7
Yashima Y(2007)Next Generation Video Coding Technologies for Ultra Realistic CommunicationIEICE Communications Society Magazine10.1587/bplus.2007.2_1412007:2(2_141-2_166)Online publication date: 2007
https://doi.org/10.1587/bplus.2007.2_141
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Index Terms

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture
1. Computing methodologies
  1. Computer graphics
    1. Image compression
2. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1999

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DATE99

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DATE99: Design Automation and Test in Europe Conference and Exhibition 1999

Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

NAKAMURA KOMORI YKOBAYASHI DNITTA KSANO KSATO MIWASAKI HKOBAYASHI H(2023)An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding ArchitectureIEICE Transactions on Electronics10.1587/transele.2022LHP0002E106.C:6(312-320)Online publication date: 1-Jun-2023
https://doi.org/10.1587/transele.2022LHP0002
Yoshitome TNakamura KKamikura K(2010)A Flexible Super High Resolution Video CODEC and Its Trial ExperimentsHigh-Quality Visual Experience10.1007/978-3-642-12802-8_7(177-195)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12802-8_7
Yashima Y(2007)Next Generation Video Coding Technologies for Ultra Realistic CommunicationIEICE Communications Society Magazine10.1587/bplus.2007.2_1412007:2(2_141-2_166)Online publication date: 2007
https://doi.org/10.1587/bplus.2007.2_141
Iwasaki HNaganuma JNitta KNakamura KYoshitome TOgura MNakajima YTashiro YOnishi TIkeda MEndo M(2003)Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV LevelProceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 210.5555/1022685.1022917Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/1022685.1022917
Iwasaki HOchiai KNaganuma JEndo MOgura T(2002)Advanced concurrent design environment for multimedia system LSIsSystems and Computers in Japan10.1002/scj.1000433:14(72-80)Online publication date: 23-Oct-2002
https://doi.org/10.1002/scj.10004
Ochiai KIwasaki HNaganuma JEndo MOgura T(1999)High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalabilityProceedings of the conference on Design, automation and test in Europe10.1145/307418.307510(63-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307510
Ochiai KIwasaki HNaganuma JEndo MOgura T(1999)High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalabilityDesign, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)10.1109/DATE.1999.761138(303-308)Online publication date: 1999
https://doi.org/10.1109/DATE.1999.761138

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MPEG 2-Based Video Coding with Three-Layer Mixed Scalability