Article

Improved crosstalk modeling for noise constrained interconnect optimization

Authors:

David Zhigang Pan,

Prasanna V. SrinivasAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Pages 373 - 378

https://doi.org/10.1145/370155.370414

Published: 30 January 2001 Publication History

Abstract

This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-pie model, and applies it to noise-constrained interconnect optimizations. Compared with previous crosstalk noise models of similar complexity, our 2-pie model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver), and the coarse distributed RC characteristics for victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width, so it is very useful for noise-aware layout optimizations. In particular, we demonstrate its effectiveness in two applications: (i) Optimization rule generation for noise reduction using various interconnect optimization techniques; (ii) Simultaneous wire spacing to multiple nets for noise constrained interconnect minimization.

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Cited By

Kumari BSharma RSahoo M(2022)Performance and reliability improvement in intercalated MLGNR interconnects using optimized aspect ratioScientific Reports10.1038/s41598-022-05222-x12:1Online publication date: 27-Jan-2022
https://doi.org/10.1038/s41598-022-05222-x
Sayil SSayil S(2022)Modeling and Prediction of Crosstalk NoiseNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_3(47-62)Online publication date: 1-Sep-2022
https://doi.org/10.1007/978-3-031-12751-9_3
Kison CAwad OFyrbiak MPaar C(2019)Security Implications of Intentional Capacitive CrosstalkIEEE Transactions on Information Forensics and Security10.1109/TIFS.2019.290091414:12(3246-3258)Online publication date: 1-Dec-2019
https://dl.acm.org/doi/10.1109/TIFS.2019.2900914
Show More Cited By

Index Terms

Improved crosstalk modeling for noise constrained interconnect optimization

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cover image ACM Conferences

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 January 2001

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Kumari BSharma RSahoo M(2022)Performance and reliability improvement in intercalated MLGNR interconnects using optimized aspect ratioScientific Reports10.1038/s41598-022-05222-x12:1Online publication date: 27-Jan-2022
https://doi.org/10.1038/s41598-022-05222-x
Sayil SSayil S(2022)Modeling and Prediction of Crosstalk NoiseNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_3(47-62)Online publication date: 1-Sep-2022
https://doi.org/10.1007/978-3-031-12751-9_3
Kison CAwad OFyrbiak MPaar C(2019)Security Implications of Intentional Capacitive CrosstalkIEEE Transactions on Information Forensics and Security10.1109/TIFS.2019.290091414:12(3246-3258)Online publication date: 1-Dec-2019
https://dl.acm.org/doi/10.1109/TIFS.2019.2900914
Das SPandit SDas D(2019)Crosstalk Aware Global Routing of Graphene Nanoribbon Based Circuits2019 IEEE 19th International Conference on Nanotechnology (IEEE-NANO)10.1109/NANO46743.2019.8993935(243-248)Online publication date: Jul-2019
https://doi.org/10.1109/NANO46743.2019.8993935
Erdemir SOruc A(2016)Noise analysis of on-chip flexing crossbars with a geometric model2016 IEEE International Symposium on Electromagnetic Compatibility (EMC)10.1109/ISEMC.2016.7571695(478-484)Online publication date: Jul-2016
https://doi.org/10.1109/ISEMC.2016.7571695
Bang SHan KKahng ALuo M(2016)Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428093(697-704)Online publication date: Jan-2016
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Martins RLourenço NHorta NMartins RLourenço NHorta N(2016)Empirical-Based Parasitic ExtractorAnalog Integrated Circuit Design Automation10.1007/978-3-319-34060-9_7(137-155)Online publication date: 21-Jul-2016
https://doi.org/10.1007/978-3-319-34060-9_7
Kahng AKang SLee H(2013)Smart non-default routing for clock power reductionProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488846(1-7)Online publication date: 29-May-2013
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Maheshwari VJha SKhare KKar RMandal D(2013)Accurate crosstalk analysis for RLCG on-chip VLSI global interconnect2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES10.1109/CICT.2013.6558106(281-286)Online publication date: Apr-2013
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Roca AHernáNdez CFlich JSilla FDuato J(2013)Silicon-aware distributed switch architecture for on-chip networksJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.03.00859:7(505-515)Online publication date: 1-Aug-2013
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