Article

Pre-layout prediction of interconnect manufacturability

Authors:

Phillip Christie,

José Pineda de GyvezAuthors Info & Claims

SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction

Pages 167 - 173

https://doi.org/10.1145/368640.368826

Published: 01 March 2001 Publication History

Abstract

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.

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Cited By

Atghiaee AMasoumi NZarkesh-Ha PMehri M(2014)Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.224384922:2(438-443)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2243849
Atghiaee AMasoumi N(2011)A Predictive and Accurate Interconnect Density FunctionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205394619:9(1704-1717)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2053946
Ghaida RDoniger KZarkesh-Ha P(2009)Random Yield Prediction Based on a Stochastic Layout Sensitivity ModelIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2009.202482122:3(329-337)Online publication date: Aug-2009
https://doi.org/10.1109/TSM.2009.2024821
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Index Terms

Pre-layout prediction of interconnect manufacturability

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Published In

cover image ACM Conferences

SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction

March 2001

178 pages

ISBN:1581133154

DOI:10.1145/368640

Chairmen:
Phillip Christie
Univ. of Delaware
,
Jeffrey Davis
Georgia Institute of Technology, Atlanta
,
Dennis Sylvester
Univ. of Michigan

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 March 2001

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SLIP01: The 3rd ACM/SIGDA International Workshop on System Level Interconnect Prediction

March 31 - April 1, 2001

California, Sonoma, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Atghiaee AMasoumi NZarkesh-Ha PMehri M(2014)Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.224384922:2(438-443)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2243849
Atghiaee AMasoumi N(2011)A Predictive and Accurate Interconnect Density FunctionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205394619:9(1704-1717)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2053946
Ghaida RDoniger KZarkesh-Ha P(2009)Random Yield Prediction Based on a Stochastic Layout Sensitivity ModelIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2009.202482122:3(329-337)Online publication date: Aug-2009
https://doi.org/10.1109/TSM.2009.2024821
Ghaida RZarkesh-Ha P(2009)A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow InterconnectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-008-5079-x25:1(67-77)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1007/s10836-008-5079-x
Atghiaee AMasoumi N(2008)Predictive Estimation for Distribution of Interconnects2008 12th IEEE Workshop on Signal Propagation on Interconnects10.1109/SPI.2008.4558403(1-4)Online publication date: May-2008
https://doi.org/10.1109/SPI.2008.4558403
Zarkesh-Ha PDoniger KKennings AMandoiu I(2007)Stochastic interconnect layout sensitivity modelProceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231959(9-14)Online publication date: 17-Mar-2007
https://dl.acm.org/doi/10.1145/1231956.1231959
Ghaida RZarkesh-Ha P(2007)Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)10.1109/DFT.2007.12(59-67)Online publication date: Sep-2007
https://doi.org/10.1109/DFT.2007.12
Zarkesh-Ha PDoniger KLoh WBendix PScheffer LMarkov I(2004)Prediction of interconnect adjacency distributionProceedings of the 2004 international workshop on System level interconnect prediction10.1145/966747.966767(99-106)Online publication date: 14-Feb-2004
https://dl.acm.org/doi/10.1145/966747.966767
Zarkesh-Ha PDoniger KLoh WWright PSylvester DStroobandt DScheffer LZarkesh-Ha P(2003)Prediction of interconnect pattern density distributionProceedings of the 2003 international workshop on System-level interconnect prediction10.1145/639929.639946(85-91)Online publication date: 5-Apr-2003
https://dl.acm.org/doi/10.1145/639929.639946
Wildman RKramer JWeile DChristie P(2003)Multi-objective optimization of interconnect geometryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80846011:1(15-23)Online publication date: 1-Feb-2003
https://dl.acm.org/doi/10.1109/TVLSI.2002.808460
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