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Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures

Published: 19 June 2024 Publication History

Abstract

In this paper, we focus on Software Programmable Streaming Coarse-Grained Reconfigurable Architectures (SPS-CGRAs). Current models fail to capture their programmability and often inaccurately estimate latency by ignoring configuration costs and latency propagation. We propose a comprehensive modeling framework using a graph-based hardware model that accounts for processing, memory access, and configuration control, all parameterized by latency.

References

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Karol Desnos and Julien Heulot. 2014. PiSDF: Parameterized & Interfaced Synchronous Dataflow for MPSoCs Runtime Reconfiguration. In 1st Workshop on MEthods and TOols for Dataflow PrOgramming (METODO). ECSI, Madrid, Spain. https://hal.science/hal-01075114
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C. Farabet et al.2011. NeuFlow: A runtime reconfigurable dataflow processor for vision. In CVPR 2011 WORKSHOPS. 109–116.
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Jan Bartovsky et al.2015. Morphological Co-Processing Unit for Embedded Devices. Journal of Real-Time Image Processing (July 2015), pp. 1–12.
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Leibo Liu et al.2019. A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. 52 (2019), 118:1–118:39.
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Rajeev, A. C. et al.2010. Schedulability and End-to-End Latency in Distributed ECU Networks: Formal Modeling and Precise Estimation. In Proceedings of the Tenth ACM International Conference on Embedded Software (Scottsdale, Arizona, USA) (EMSOFT ’10). Association for Computing Machinery, New York, NY, USA, 129–138. https://doi.org/10.1145/1879021.1879039
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Paulo Possa, Naim Harb, Eva Dokládalová, and Carlos Valderrama. 2015. P2IP. Microprocess. Microsyst. 39, 7 (Oct. 2015), 529–540.

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  1. Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures

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      HEART '24: Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
      June 2024
      147 pages
      Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 19 June 2024

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      Author Tags

      1. Coarse-Grained Reconfigurable Architecture
      2. Hardware
      3. Latency.
      4. Modeling
      5. Software Programmable Streaming CGRA

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      Overall Acceptance Rate 22 of 50 submissions, 44%

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