A Domain Specific Computing Architecture for Open 6G Baseband Signal Processing

The vision of decoupled software and hardware for wireless communications has prompted the application of Open-Radio-Access-Networks (O-RANs) and Software Defined Radios (SDRs). Such a structure is beneficial to operators for flexible and low-cost network deployment, and to terminals for continuously evolving wireless technologies. Conventionally, they rely on General-Purpose-Processors (GPPs) such as Intel’s x86 processors, Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) for digital baseband signal processing. However, concerns regarding energy efficiency, open software environment and programmability still hinder the development. This paper proposes a domain specific manycore architecture based on RISC-V instruction extension and a multi-level dataflow programming model for open-source baseband signal processing in 6G networks. The proposed architecture shows promising performance which is comparable to state-of-the-art FPGA implementations, and meanwhile flexibility in terms of software programmability.